Input/Output Pins; Renesas Spdif (Iec60958) Frame Format - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.4

Input/Output Pins

Table 23.1 shows the pin configuration.
Table 23.1 Pin Configuration
Channel Pin Name
0 SPDIF_OUT
1 SPDIF_IN
0, 1 AUDIO_CLK
(Common)
AUDIO_X1
AUDIO_X2
23.5

Renesas SPDIF (IEC60958) Frame Format

The Renesas SPDIF frame consists of two subframes (for channels 1 and 2), each of which contains a 4-bit preamble,
audio data of up to 24 bits, a V flag, a user bit, a channel status bit, and an even parity bit. Figure 23.3 shows the
subframe format. According to this format, the Renesas SPDIF performs biphase-mark modulation (channel coding) that
will make the transmission line's DC component a minimum value.
0
Synchronization
preamble
B/M/W
Figure 23.3 Subframe Format
Figure 23.4 shows the block format, which consists of 192 continuous frames. One block begins at the starting frame
(preamble B) and ends at the 192nd frame (frame 191), and the preamble is used to identify all subframes. Each block
has a total of 384 subframes, which are classified into three categories: subframe 0 indicating the beginning of a new
block, subframe 1 (usually the channel 1), and subframe 2 (usually the channel 2). Usually, the music data sent and
received by the SPDIF is continuous so that continuous blocks appear.
0
B
Channel 1
Figure 23.4 Block Format
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
I/O
Output
Input
Input
Input
Output
3 4 7 8
L L
S Aux S
B B
1
W M
Channel 2 Channel 1
B = Start of block preamble
W = Channel 2 preamble
M = Channel 1 preamble but not start of block
Description
Transmitter biphase-mark encoded SPDIF bitstream
Receiver biphase-mark encoded SPDIF bitstream
External clock for audio
Crystal resonator/external clock for audio
Audio sample word
V = Validity flag
U = User data
C = Channel status
P = Parity bit
191 0
M W B
Channel 1 Channel 2 Channel 1
23. Renesas SPDIF Interface
27 28 31
M
S V U C P
B
1
W M
Channel 2 Channel 1
23-3