Data Format - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.4.5

Data Format

The data format depends on the settings in the command register (SPCMD). Irrespective of MSB/LSB first, this module
treats the range from the LSB of the data register (SPDR) to the assigned data length as transfer data.
(1) MSB First Transfer (32-Bit Data)
Figure 16.8 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs a 32-bit
data length MSB-first data transfer.
The CPU or direct memory access controller writes T31 to T00 to the transmit buffer of SPDR. If the shift register is
empty, this module copies the data in the transmit buffer to the shift register, and fully populates the shift register. When
serial transfer starts, this module outputs data from the MSB (bit 31) in the shift register, and shifts in the data from the
LSB (bit 0) in the shift register. When the RSPCK cycle required for the serial transfer of 32 bits has passed, data R31 to
R00 is stored in the shift register. In this state, this module copies the data from the shift register to the receive buffer, and
empties the shift register. If the receive buffer does not have a space for the receive data length after the receive data has
been copied from the shift register to the receive buffer, another serial transfer will not be started. In order to start another
serial transfer, data for the receive data length should be read from the receive buffer to secure the necessary space in the
receive buffer.
If another serial transfer is started before the CPU or direct memory access controller writes to the transmit buffer,
received data R31 to R00 is shifted out from the shift register.
Transfer start
Bit 31
T31 T30 T29 T28 T27 T26 T25 T24 T23
Output
T31 T30 T29 T28 T27 T26 T25 T24 T23
Bit 31
Transfer end
Bit 31
R31 R30 R29 R28 R27 R26 R25 R24 R23
R31 R30 R29 R28 R27 R26 R25 R24 R23
Bit 31
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 16.8 MSB First Transfer (32-Bit Data)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Transmit buffer (SPTX)
T08 T07 T06 T05 T04 T03 T02 T01 T00
Copy
T08 T07 T06 T05 T04 T03 T02 T01 T00
Shift register
Shift register
R08 R07 R06 R05 R04 R03 R02 R01 R00
Copy
R08 R07 R06 R05
Receive buffer (SPRX)
16. Renesas Serial Peripheral Interface
Bit 0
Bit 0
Bit 0
Input
R04 R03 R02 R01 R00
Bit 0
16-26