Interrupts - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.5

Interrupts

This module has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive FIFO data full
(RXI), and break (BRI).
Table 14.12 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by
means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each
of these interrupt sources.
When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register (SCFSR) is set to 1, a TXI
interrupt request is generated. The direct memory access controller can be activated and data transfer performed by this
TXI interrupt request. At this time, an interrupt request is not sent to the CPU.
When an RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set to 1, an RXI interrupt
request is generated. The direct memory access controller can be activated and data transfer performed by this RXI
interrupt request. At this time, an interrupt request is not sent to the CPU. The RXI interrupt request caused by the DR
flag is generated only in asynchronous mode.
When the RIE bit is set to 0 and the REIE bit is set to 1, this module requests only an ERI or a BRI interrupt without
requesting an RXI interrupt.
The TXI indicates that transmit data can be written, and the RXI indicates that there is receive data in SCFRDR.
Table 14.12 Interrupt Sources
Interrupt
Source Description
BRI Interrupt initiated by break (BRK) or overrun error (ORER)
ERI Interrupt initiated by receive error (ER)
RXI Interrupt initiated by receive FIFO data full (RDF) or data ready (DR)
TXI Interrupt initiated by transmit FIFO data empty (TDFE)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14. Serial Communication Interface with FIFO
Direct Memory Access
Controller Activation
Not possible
Not possible
Possible
Possible
Priority on Reset
Release
High
Low
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