Control Register (Ssicr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.3.1

Control Register (SSICR)

SSICR is a 32-bit readable/writable register that controls the IRQ, selects the polarity status, and sets operating mode.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
SCKD SWSD
Initial value:
0
R/W: R/W
Bit Bit Name
31 ―
30 CKS
29 TUIEN
28 TOIEN
27 RUIEN
26 ROIEN
25 IIEN
24 ―
23, 22 CHNL[1:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
CKS TUIEN TOIEN RUIEN ROIEN
0 0 0 0 0
R/W R/W R/W R/W R/W
14 13 12 11 10
SCKP SWSP SPDP SDTA
0 0 0 0 0
R/W R/W R/W R/W R/W
Initial
Value R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
00 R/W
25 24 23 22 21
IIEN - CHNL[1:0]
0 0 0 0
R/W R R/W R/W R/W
9 8 7 6
PDTA DEL CKDV[3:0]
0 0 0 0
R/W R/W R/W R/W R/W
Description
Reserved
The read value is undefined. The write value should always be 0.
Oversampling Clock Select
Selects the clock source for oversampling.
0: AUDIO_X1 input
1: AUDIO_CLK input
Transmit Underflow Interrupt Enable
0: Disables an underflow interrupt.
1: Enables an underflow interrupt.
Transmit Overflow Interrupt Enable
0: Disables an overflow interrupt.
1: Enables an overflow interrupt.
Receive Underflow Interrupt Enable
0: Disables an underflow interrupt.
1: Enables an underflow interrupt.
Receive Overflow Interrupt Enable
0: Disables an overflow interrupt.
1: Enables an overflow interrupt.
Idle Mode Interrupt Enable
0: Disables an idle mode interrupt.
1: Enables an idle mode interrupt.
Reserved
The read value is undefined. The write value should always be 0.
Channels
[When TDM = 0]
These bits show the number of channels in each system word.
00: Having one channel per system word
01: Having two channels per system word
10: Having three channels per system word
11: Having four channels per system word
[When TDM = 1]
These bits show the number of system words in each TDM frame.
00: Setting prohibited
01: Having four system words per TDM frame
10: Having six system words per TDM frame
11: Having eight system words per TDM frame
19. Serial Sound Interface
20 19 18 17
DWL[2:0] SWL[2:0]
0 0 0 0 0
R/W R/W R/W R/W
5 4 3 2 1
MUEN - TEN
0 0 0 0 0
R/W R/W R R/W
16
0
R/W
0
REN
0
R/W
19-6