Axi Bus Control Register 2 (Axibusctl2); Axi Bus Control Register 5 (Axibusctl5) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.3

AXI Bus Control Register 2 (AXIBUSCTL2)

This register controls the cache operation for the capture engine unit.
Bit: 31
—
Initial value:
0
R/W:
R
Bit: 15
—
Initial value:
0
R/W:
R
Bit Bit Name
31 to 4 —
3 to 0 CEUAWCA
CHE
[3:0]
5.10.4

AXI Bus Control Register 5 (AXIBUSCTL5)

This register is only provided in the RZ/A1L.
This register controls the cache operation for the media local bus.
Bit: 31
—
Initial value:
0
R/W: R
Bit:
15
—
Initial value:
0
R/W: R
Bit Bit Name
31 to 2 —
1, 0 MLBAXCA
CHE
[1:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
— — — — —
0 0 0 0 0
R R R R R
14 13 12 11 10
— — — — —
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0000 R/W AWCACHE[3:0] Signals for Capture Engine Unit
These bits specify the system cache operation when capture engine unit performs
write access. The values of these bits are used as the AWCACHE[3:0] signals for
capture engine unit. Modify the values of these bits only while capture engine unit
does not use the internal bus.
30 29 28 27 26
— — — — —
0 0 0 0 0
R R R R R
14 13 12 11 10
— — — — —
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
00 R/W AWCACHE[3:0] and ARCACHE[3:0] Signals for Media Local Bus
These bits specify the system cache operation when the media local bus performs
read or write access. The values of these bits are used as the AWCACHE[3:0] and
ARCACHE[3:0] signals for the media local bus.
The MLBAXCACHE[0] value is used as ARCACHE[0] and AWCACHE[0] without
change.
When MLBAXCACHE[1] = 0, the ARCACHE[3:1] and AWCACHE[3:1] signals are all
set to 0.
When MLBAXCACHE[1] = 1, the ARCACHE[3:1] and AWCACHE[3:1] signals are all
set to 1.
Modify the values of these bits only while the media local bus does not use the
internal bus.
25 24 23 22 21
— — — — —
0 0 0 0 0
R R R R R
9 8 7 6 5
—
— — — —
0 0 0 0 0
R R R R R
25 24 23 22 21
— — — — —
0 0 0 0 0
R R R R R
9 8 7 6 5
—
— — — —
0 0 0 0 0
R R R R R
5. LSI Internal Bus
20 19 18 17 16
— — — — —
0 0 0 0 0
R R R R R
4 3 2 1 0
—
CEUAWCACHE[3:0]
0 0 0 0 0
R R/W R/W R/W R/W
20 19 18 17 16
— — — — —
0 0 0 0 0
R R R R R
4 3 2 1 0
MLBAXCACHE
— — —
[1:0]
0 0 0 0 0
R R R R/W R/W
5-17