Timer Start Register (Tstr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.13

Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bit Bit Name
7 CST4
6 CST3
5 to 3 —
2 CST2
1 CST1
0 CST0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit:
7 6
CST4 CST3
Initial value:
0 0
R/W:
R/W R/W
Initial
Value R/W Description
0 R/W Counter Start 4 and 3
These bits select operation or stoppage for TCNT.
0 R/W
If 0 is written to the CST bit during operation with the TIOC pin designated for
output, the counter stops but the TIOC pin output compare output level is
retained. If TIOR is written to when the CST bit is cleared to 0, the pin output
level will be changed to the set initial output value.
0: TCNT_4 and TCNT_3 count operation is stopped
1: TCNT_4 and TCNT_3 performs count operation
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Counter Start 2 to 0
These bits select operation or stoppage for TCNT.
0 R/W
If 0 is written to the CST bit during operation with the TIOC pin designated for
0 R/W
output, the counter stops but the TIOC pin output compare output level is
retained. If TIOR is written to when the CST bit is cleared to 0, the pin output
level will be changed to the set initial output value.
0: TCNT_2 to TCNT_0 count operation is stopped
1: TCNT_2 to TCNT_0 performs count operation
5 4 3 2 1
- - - CST2 CST1
0 0 0 0 0
R R R R/W R/W
10. Multi-Function Timer Pulse Unit 2
0
CST0
0
R/W
10-42