Riicndrr - I²C Bus Receive Data Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.15 RIICnDRR — I²C Bus Receive Data Register
Access: RIICnDRR is a 32-bit readable/writable register.
RIICnDRRL and RIICnDRRH are 16-bit readable/writable registers.
RIICnDRRLL, RIICnDRRLH, RIICnDRRHL, and RIICnDRRHH are 8-bit readable/writable registers.
Address: RIICnDRR: <RIICn_base> + 0040
RIICnDRRL: <RIICn_base> + 0040
RIICnDRRLL: <RIICn_base> + 0040
RIICnDRRHH: <RIICn_base> + 0043
Initial Value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
When 1 byte of data has been received, the received data is transferred from the I
(RIICnDRS) to RIICnDRR to enable the next data to be received.
The double-buffer structure of RIICnDRS and RIICnDRR allows continuous receive operation if the
received data has been read from RIICnDRR while RIICnDRS is receiving data.
RIICnDRR cannot be written. Read data from RIICnDRR once when a receive data full interrupt
(INTRIICRI) request is generated.
If DRR receives the next receive data before the current data is read from RIICnDRR (while the
RIICnSR2.RDRF flag is 1), the RIIC automatically holds the SCL clock low one cycle before the
RDRF flag is set to 1 next.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnDRRH: <RIICn_base> + 0042
H
, RIICnDRRLH: <RIICn_base> + 0041
H
H
This register is initialized by any reset.
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
H
, RIICnDRRHL: <RIICn_base> + 0042
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— —
0 0 0 0
R R R R
18. I²C Bus Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
DRR[7:0]
0 0 0 0
R R R R
2
C bus shift register
,
H
17 16
— —
0 0
R R
1 0
0 0
R R
18-42