Timer Status Register (Tsr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.5

Timer Status Register (TSR)

The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. This module has six TSR
registers, two for channel 0 and one each for channels 1 to 4.
• TSR_0, TSR_1, TSR_2, TSR_3, TSR_4
Note:
Bit Bit Name
7 TCFD
6 —
5 TCFU
4 TCFV
3 TGFD
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit:
7 6
TCFD - TCFU
Initial value:
1 1
R/W:
R R R/(W)*
1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Value R/W Description
1 R Count Direction Flag
Status flag that shows the direction in which TCNT counts in channels 1 to 4.
In channel 0, bit 7 is reserved. It is always read as 1 and the write value should
always be 1.
0: TCNT counts down
1: TCNT counts up
1 R Reserved
This bit is always read as 1. The write value should always be 1.
1
0 R/(W)* Underflow Flag
Status flag that indicates that TCNT underflow has occurred when channels 1
and 2 are set to phase counting mode. Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write
value should always be 0.
[Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1*
[Setting condition]
• When the TCNT value underflows (changes from H'0000 to H'FFFF)
1
0 R/(W)* Overflow Flag
Status flag that indicates that TCNT overflow has occurred. Only 0 can be
written, for flag clearing.
[Clearing condition]
• When 0 is written to TCFV after reading TCFV = 1*
[Setting condition]
• When the TCNT value overflows (changes from H'FFFF to H'0000)
In channel 4, when the TCNT_4 value underflows (changes from H'0001 to
H'0000) in complementary PWM mode, this flag is also set.
1
0 R/(W)* Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input capture or compare
match in channels 0, 3, and 4.
Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is
always read as 0 and the write value should always be 0.
[Clearing condition]
• When 0 is written to TGFD after reading TGFD = 1*
[Setting conditions]
• When TCNT = TGRD and TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal and TGRD
is functioning as input capture register
5 4 3 2 1
TCFV TGFD TGFC TGFB
0 0 0 0 0
1 1 1 1
R/(W)* R/(W)* R/(W)* R/(W)*
10. Multi-Function Timer Pulse Unit 2
0
TGFA
0
1 1
R/(W)*
2
2
2
10-33