Mpx-I/O Interface - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.5.5

MPX-I/O Interface

Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WEn signals control the
accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal
space. The bus width for the address output cycle or the data input/output cycle is fixed to 8 bits or 16 bits. Alternatively,
it can be 8 bits or 16 bits depending on the address to be accessed.
Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3. Because cycle Ta1 has a high-
impedance state, collisions of addresses and data can be avoided without inserting idle cycles, even in continuous access
cycles. Address output is increased to 3 cycles by setting the MPXW bit in CS5WCR to 1.
The RD/WR signal is output at the same time as the CS5 signal; it is high in the read cycle and low in the write cycle.
The data cycle is the same as that in a normal space access.
The delay cycles the number of which is specified by SW[1:0] are inserted between cycle Ta3 and cycle T1. The delay
cycles the number of which is specified by HW[1:0] are added after cycle T2.
Timing charts are shown in Figure 8.11 to Figure 8.13.
Read
D15/D7 to D0
Write
D15/D7 to D0
Figure 8.11 (1) Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Ta1
CKIO
A25 to A0
CS5
RD/WR
AH
RD
WEn
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Ta2 Ta3 T1
Address
Address
8. Bus State Controller
T2
Data
Data
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