Rscan0Gaflp0J - Receive Rule Pointer 0 Register (J = 0 To 15) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.15 RSCAN0GAFLP0j — Receive Rule Pointer 0 Register (j = 0 to 15)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0508
Initial value: 0000 0000
Bit 31 30 29
GAFLDLC[3:0]
Initial value 0 0 0
R/W R/W R/W R/W
Bit 15 14 13
GAFLR
MV
0 0 0
Initial value
R/W R/W R/W R/W
Table 21.29
Bit Position
31 to 28
27 to 16
15
14 to 8
7 to 0
Modify the RSCAN0GAFLP0j register when the AFLDAE bit in the RSCAN0GAFLECTR register is
set to 1 (receive rule table write is enabled) in global reset mode.
GAFLDLC[3:0] Bits
These bits are used to set the minimum data length necessary for receiving messages. If the data length
of a message that is being filtered is equal to or larger than the value set by the GAFLDLC[3:0] bits, the
message passes the DLC check. Setting these bits to 0000
messages with any data length to pass the DLC check.
GAFLPTR[11:0] Bits
These bits are used to set a 12-bit label to be attached to messages that have passed through the filter. A
label is attached when a message is stored in the receive buffer or the FIFO buffer.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (j * 0010 )
H H
H
28 27 26
0 0 0
R/W R/W R/W
12 11 10
GAFLRMDP[6:0]
0 0 0
R/W R/W R/W
RSCAN0GAFLP0j register contents
Bit Name Function
GAFLDLC[3:0] Receive Rule DLC
b31 b30 b29 b28
GAFLPTR[11:0] Receive Rule Label
Set the 12-bit label information.
GAFLRMV Receive Buffer Enable
GAFLRMDP[6:0] Receive Buffer Number Select
Set the receive buffer number to store receive messages.
Reserved These bits are always read as 0. The write value should always be 0.
25 24 23 22
GAFLPTR[11:0]
0 0 0 0
R/W R/W R/W R/W
9 8 7 6
— —
0 0 0 0
R/W R/W R R
0 0 0 0: DLC check is disabled.
0 0 0 1: 1 data byte
0 0 1 0: 2 data bytes
0 0 1 1: 3 data bytes
0 1 0 0: 4 data bytes
0 1 0 1: 5 data bytes
0 1 1 0: 6 data bytes
0 1 1 1: 7 data bytes
1 X X X: 8 data bytes
0: No receive buffer is used.
1: A receive buffer is used.
B
21 20 19 18
0 0 0 0
R/W R/W R/W R/W
5 4 3 2
— — — —
0 0 0 0
R R R R
disables the DLC check function allowing
21. CAN Interface
17 16
0 0
R/W R/W
1 0
— —
0 0
R R
21-48