Axi Bus Response Error Status Register 0 (Axirerrst0) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.9

AXI Bus Response Error Status Register 0 (AXIRERRST0)

This register indicates occurrence of AXI bus response errors.
Bit:
31
JCURRESP
[1:0]*
Initial value:
0
R/W: R
Bit:
15
—
Initial value: 0
R/W: R
Bit Bit Name
31, 30 JCURRESP
[1:0]*
29, 28 JCUBRESP
[1:0]*
27, 26 ETHRRES
P[1:0]
25, 24 ETHBRESP
[1:0]
23 to 10 —
9, 8 CEUBRES
P[1:0]
7 to 0 —
Note: * These bits are only present in the RZ/A1LU. For the RZ/A1L and RZ/A1LC, these bits are always read as 0. The write
value should always be 0.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
JCUBRESP
ETHRRESP
[1:0]* [1:0]
0 0 0 0 0
R R R R R
14 13 12 11 10
— — — — —
0 0 0 0 0
R R R R R
Initial
Value R/W Description
00 R RRESP[1:0] Signals for JPEG Codec Unit
These bits indicate the RRESP[1:0] signals received by the JPEG codec unit. The
values of these bits are updated when a response error occurs.
00: OKAY
10: SLVERR
11: DECERR
00 R BRESP[1:0] Signals for JPEG Codec Unit
These bits indicate the BRESP[1:0] signals received by the JPEG codec unit. The
values of these bits are updated when a response error occurs.
00: OKAY
10: SLVERR
11: DECERR
00 R RRESP[1:0] Signals for Ethernet Controller
These bits indicate the RRESP[1:0] signals received by the Ethernet controller. The
values of these bits are updated when a response error occurs.
00: OKAY
10: SLVERR
11: DECERR
00 R BRESP[1:0] Signals for Ethernet Controller
These bits indicate the BRESP[1:0] signals received by the Ethernet controller. The
values of these bits are updated when a response error occurs.
00: OKAY
10: SLVERR
11: DECERR
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
00 R BRESP[1:0] Signals for Capture Engine Unit
These bits indicate the BRESP[1:0] signals received by capture engine unit. The
values of these bits are updated when a response error occurs.
00: OKAY
10: SLVERR
11: DECERR
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
25 24 23 22 21
ETHBRESP
—
— —
[1:0]
0 0 0 0 0
R R R R R
9 8 7 6 5
CEUBRESP
—
— —
[1:0]
0 0 0 0 0
R R R R R
5. LSI Internal Bus
20 19 18 17 16
—
— — — —
0 0 0 0 0
R R R R R
4 3 2 1 0
—
— — — —
0 0 0 0 0
R R R R R
5-22