Rscan0Cfpctrk - Transmit/Receive Fifo Buffer Pointer Control Register (K = 0 To 5) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.32 RSCAN0CFPCTRk — Transmit/receive FIFO buffer Pointer Control Register
(k = 0 to 5)
Access: Can be written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 01D8
Initial value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.46
Bit Position
31 to 8
7 to 0
CFPC[7:0] Bits
• Receive mode (CFM[1:0] value in the RSCAN0CFCCk register is 00
Writing FF
transmit/receive FIFO buffer. At this time, the CFMC[7:0] value (transmit/receive FIFO message
counter) in the RSCAN0CFSTSk register is decremented. Read the RSCAN0CFIDk,
RSCAN0CFPTRk, RSCAN0CFDF0k, and RSCAN0CFDF1k registers to read messages from the
transmit/receive FIFO buffer, and then write FF
Write FF
receive FIFO buffers are used) and the CFEMP flag in the RSCAN0CFSTSk register is cleared to
0 (the transmit/receive FIFO buffer contains messages).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (k * 0004 )
H H
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RSCAN0CFPCTRk register contents
Bit Name Function
Reserved The write value should always be 0.
CFPC[7:0] Transmit/Receive FIFO Pointer Control
• Receive mode:
• Transmit mode:
• Gateway mode:
to the CFPC[7:0] bits moves the read pointer to the next unread message in the
H
to these bits when the CFE bit in the RSCAN0CFCCk register is set to 1 (transmit/
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— —
0 0 0 0
R R W W
Writing FF to these bits moves the read pointer to the next unread
H
message in the transmit/receive FIFO buffer.
Writing FF to these bits moves the write pointer to the next stage of the
H
transmit/receive FIFO buffer.
Setting prohibited
to the CFPC[7:0] bits.
H
21. CAN Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
CFPC[7:0]
0 0 0 0
W W W W
):
B
17 16
— —
0 0
R R
1 0
0 0
W W
21-73