Frequency Register H/L (Rfrh/L) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
13.3.20

Frequency Register H/L (RFRH/L)

RFRH/L is a 16-bit readable/writable register.
The "frequency comparison value" is set in RFC[18:0] so that a 128-Hz clock is generated when the realtime clock
operates at the EXTAL clock frequency.
Change the "frequency comparison value" according to the EXTAL clock frequency. The calculation method is shown
below. When the RCKSEL bits in RCR5 are set to 00, setting this register is not necessary.
Bit: 31
SEL64
Initial value:
Undefined
R/W: R/W
Bit:
15
Initial value:
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
Bit Bit Name
31 SEL64
—
30 to 19
18 to 0 RFC[18:0]
(1) Method for calculating "frequency comparison value".
• When EXTAL clock frequency is dividable by 128 Hz:
RFC[18:0] = (EXTAL clock frequency)/128
Clear the SEL64 bit to 0.
• When EXTAL clock frequency is not dividable by 128 Hz but is dividable by 64 Hz:
RFC[18:0] = (EXTAL clock frequency)/64
Set the SEL64 bit to 1.
(2) Setting Example
Table 13.3 Setting Example
Clock Frequency
EXTAL
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
R/W R/W R/W R/W R/W
Initial
Value R/W Description
Undefined R/W 64-Hz Divider Select
Indicates the EXTAL clock frequency is not dividable by 128 Hz but is dividable
by 64 Hz.
0: EXTAL clock frequency is dividable by 128 Hz.
1: EXTAL clock frequency is not dividable by 128 Hz but is dividable by 64 Hz.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
Undefined R/W Frequency comparison value
Sets the comparison value to generate operation clock from the EXTAL clock
frequency.
10 MHz
11 MHz
12 MHz
13 MHz
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
RFC[15:0]
R/W R/W R/W R/W R/W
SEL64 Setting Value
0
1
0
1
13. Realtime Clock
20 19 18 17 16
- - RFC[18:16]
0 0
Undefined Undefined Undefined
R R R/W R/W R/W
4 3 2 1 0
R/W R/W R/W R/W R/W
RFC Setting Value
H'1312D
H'29F63
H'16E36
H'31975
13-15