Status Register (Stat) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.7.2

Status Register (STAT)

Bit Bit Name
31 to 17 ―
16 CMD
15 RIS
14 TIS
13 UBO
12 UBU
11 CE
10 PARE
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 31 30 29
- - -
Initial value: 0 0 0
R/W: R R R
Bit: 23 22 21
- - -
Initial value: 0 0 0
R/W: R R R
Bit: 15 14 13
RIS TIS UBO
Initial value: 1 1 0
R/W: R R
R/WC0 R/WC0 R/WC0 R/WC0 R/WC0 R/WC0
Bit: 7 6 5
ABO ABU RUIR TUIR CSRX
Initial value: 0 0 0
R/W: R
R/WC0 R/WC0
Initial
Value R/W Description
All 0 R Reserved
0 R Compressed Mode Data
Sets if the data being received is compressed mode data (When bit 1 = 1
in the V flag and channel status).
0: Data is not in compressed mode
1: Data is in compressed mode
1 R Receiver Idle State
Sets if the receiver is in the idle state.
0: Receiver is not in idle state
1: Receiver in idle state
1 R Transmitter Idle State
Sets if the transmitter is in the idle state.
0: Transmitter is not in idle state
1: Transmitter is in idle state
0 R/WC0 User Buffer Overrun*
Sets if the receiver user buffer overruns. This bit is cleared by writing 0 to
the register. If bit REIE and bit UBOI in the control register are set this
causes an interrupt.
0: User buffer has not overrun
1: User buffer has overrun
0 R/WC0 User Buffer Underrun*
Sets if the transmitter user buffer underrun. This bit is cleared by writing
0. If bits TEIE and UBUI in the control register are set this causes an
interrupt.
0: User buffer has not underrun
1: User buffer has underrun
0 R/WC0 Clock Error*
Sets when the clock recovery falls out of synchronization. This bit is
cleared by writing 0. If bits REIE and CREI in the control register are set
this causes an interrupt.
0: Clock recovery stable
1: Clock recovery error
0 R/WC0 Parity Error*
Sets when the parity checker produces a fail result. This bit is cleared by
writing 0. If bits REIE and PAEI in the control register are set this causes
an interrupt.
0: Parity check correct
1: Parity error
28 27 26 25 24
- - - - -
0 0 0 0 0
R R R R R
20 19 18 17 16
- - - - CMD
0 0 0 0 0
R R R R R
12 11 10 9 8
UBU CE PARE PREE CSE
0 0 0 0 0
4 3 2 1 0
CBRX CSTX CBTX
0 0 0 0 0
R R R R R
23. Renesas SPDIF Interface
23-9