Tdm Mode Register (Ssitdmr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.3.9

TDM Mode Register (SSITDMR)

SSITDMR is a 32-bit readable/writable register that enables or disables muting of receive data in direct transfer, TDM
mode, and WS continue mode.
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value: 0
R/W:
R
Bit Bit Name
31 to 18 ―
17 RXDMUTE
16 ―
15 to 9 ―
8 CONT
7 to 1 ―
0 TDM
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 R/W
0 R/W
All 0 R
0 R/W
All 0 R
0 R/W
25 24 23 22 21
- - - -
0 0 0 0
R R R R R
9 8 7 6
- CONT - -
0 0 0 0
R R/W R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Receive Direct Data Mute Setting
When receive data is output directly to the SCUX, the output data is forcibly
muted so that there is no signal (output as 0 data).
0: The receive data is output without change.
1: 0 data is output.
Reserved
Always write 0 to this bit.
Reserved
These bits are always read as 0. The write value should always be 0.
WS Continue Mode
0: Disables WS continue mode.
1: Enables WS continue mode.
Note: This bit can be set only in master mode
(SCKD = 1 and SWSD = 1)
Reserved
These bits are always read as 0. The write value should always be 0.
TDM Mode
0: Disables TDM mode.
1: Enables TDM mode.
19. Serial Sound Interface
20 19 18 17
RXD
- - - -
MUTE
0 0 0 0 0
R R R R/W
5 4 3 2 1
- - - - -
0 0 0 0 0
R R R R
16
-
0
R/W
0
TDM
0
R/W
19-18