Next-Access Delay Register (Spnd) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.3.12

Next-Access Delay Register (SPND)

SPND sets a non-active period (next-access delay) after termination of a serial transfer when the SPNDEN bit in the
command register (SPCMD) is 1. If the contents of SPND are changed while the MSTR and SPE bits in the control
register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be
guaranteed.
When using this module in slave mode, set B'000 to SPNDL2 to SPNDL0.
Bit Bit Name
7 to 3 ―
2 SPNDL2
1 SPNDL1
0 SPNDL0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6 5
⎯ ⎯ ⎯
Initial value: 0 0 0
R/W: R R R
Initial Value R/W Function
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
0 R/W Next-Access Delay Setting
0 R/W These bits set a next-access delay when the SPNDEN bit in SPCMD is 1.
0 R/W The relationship between the setting of SPNDL2 to SPNDL0 and the
next-access delay value is shown below.
000: 1 RSPCK + 2 P1 φ
001: 2 RSPCK + 2 P1 φ
010: 3 RSPCK + 2 P1 φ
011: 4 RSPCK + 2 P1 φ
100: 5 RSPCK + 2 P1 φ
101: 6 RSPCK + 2 P1 φ
110: 7 RSPCK + 2 P1 φ
111: 8 RSPCK + 2 P1 φ
16. Renesas Serial Peripheral Interface
4 3 2 1 0
⎯ ⎯ SPN SPN SPN
DL2 DL1 DL0
0 0 0 0 0
R R R/W R/W R/W
16-15