18.14 Smbus Operation; Smbus Timeout Measurement - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

18.14 SMBus Operation

The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform
SMBus communication, set the RIICnMR3.SMBS bit to 1. To use the transfer rate within a range of 10
kbps to 100 kbps of the SMBus standard, set the RIICnMR1.CKS[2:0] bits, RIICnCBRH, and
RIICnBRL. In addition, determine the values of the RIICnMR2.DLCS bit and the
RIICnMR2.SDDL[2:0] bits to meet the data hold time specification of 300 ns or more. If the RIIC is
used only as a slave device, the transfer rate setting is not necessary. When the RIIC is used only as a
slave device, the transfer rate setting is not necessary, whereas the RIICnBRL needs to be set to a value
equal to or longer than the data setup time (250 ns).
For the SMBus device default address (1100 001
(RIICnSAR0, RIICnSAR1, and RIICnSAR2), and set the corresponding RIICnSARy.FSy bit (7-bit/10-
bit address format select) (y = 0 to 2) to 0 (7-bit address format).
When transmitting the UDID (Unique Device Identifier), set the RIICnFER.SALE bit to 1 to enable the
slave arbitration lost detection function.
18.14.1

SMBus Timeout Measurement

(1) Measuring timeout of slave device
The following period (timeout interval: T
communication.
• From start condition to stop condition
To measure timeout for slave devices, measure the period from start condition detection to stop
condition detection with the internal timer using a start condition detection interrupt
(INTRIICSTI) and stop condition detection interrupt (INTRIICSPI) of the RIIC. The measured
timeout period must be within the total clock low-level period [slave device] T
(max.) of the SMBus standard.
If the time measured with the internal timer exceeds the clock low-level detection timeout
T
TIMEOUT
1 to the RIICnCR1.IICRST bit to issue an internal reset of the RIIC. When an internal reset is
issued, the RIIC stops driving the bus for the SCL pin and SDA pin and make the SCL/SDA pin
outputs high impedance, which releases the bus.
(2) Measuring timeout of master device
The following periods (timeout interval: T
communication.
• From start condition to acknowledge bit
• Between acknowledge bits
• From acknowledge bit to stop condition
To measure timeout for master devices, measure these periods with the internal timer using a start
condition detection interrupt (INTRIICSTI), stop condition detection interrupt (INTRIICSPI), and
transmit end interrupt (INTRIICTEI) or receive data full interrupt (INTRIICRI) of the RIIC. The
measured timeout period must be within the total clock low-level extended period [master device]
T
LOW: MEXT
condition to stop condition must be within T
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
: 25 ms (min.) of the SMBus standard, the slave device must release the bus by writing
: 10 ms (max.) of the SMBus standard, and the total of all T
), use one of the slave address registers L0 to L2
B
) must be measured for slave devices in SMBus
LOW: SEXT
) must be measured for master devices in SMBus
LOW: MEXT
: 25 ms (max.).
LOW: SEXT
18. I²C Bus Interface
: 25 ms
LOW: SEXT
from start
LOW: MEXT
18-88