Axi Bus Control Register 7 (Axibusctl7) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.6

AXI Bus Control Register 7 (AXIBUSCTL7)

This register controls the cache operation for video display controller 5.
Bit: 31
—
Initial value:
0
R/W:
R
Bit: 15
—
Initial value:
0
R/W:
R
Bit Bit Name
31 to 12 —
11 to 8 VDC504AR
CACHE
[3:0]
7 to 0 —
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
— — — — —
0 0 0 0 0
R R R R R
14 13 12 11 10
— — — VDC504ARCACHE[3:0]
0 0 0 0 0
R R R R/W R/W
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0000 R/W ARCACHE[3:0] Signals for Video Display Controller 5 IV6-BUS
These bits specify the system cache operation when the IV6-BUS of video display
controller 5 performs read access. The values of these bits are used as the
ARCACHE[3:0] signals for the IV6-BUS of video display controller 5. Modify the
values of these bits only while video display controller 5 does not use the internal
bus.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
25 24 23 22 21
— — — — —
0 0 0 0 0
R R R R R
9 8 7 6 5
—
— —
0 0 0 0 0
R/W R/W R R R
5. LSI Internal Bus
20 19 18 17 16
— — — — —
0 0 0 0 0
R R R R R
4 3 2 1 0
— — —
— —
0 0 0 0 0
R R R R R
5-19