Rscan0Cmsts - Channel Status Register (M = 0 Or 1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.3 RSCAN0CmSTS — Channel Status Register (m = 0 or 1)
Access: Can be read in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0008
Initial value: 0000 0005
H
Bit 31 30 29
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.17
Bit Position
31 to 24
23 to 16
15 to 8
7
6
5
4
3
2
1
0
TEC[7:0] Bits
These bits contain the transmit error counter value. For transmit error counter increment/decrement
conditions, see the CAN specification (ISO11898-1).
These bits are cleared to 0 in channel reset mode.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (m * 0010 )
H H
28 27 26 25
TEC[7:0]
0 0 0 0
R R R R
12 11 10 9
— — — —
0 0 0 0
R R R R
RSCAN0CmSTS register contents
Bit Name Function
TEC[7:0] The transmit error counter (TEC) can be read.
REC[7:0] The receive error counter (REC) can be read.
Reserved These bits are always read as 0.
COMSTS Communication Status Flag
0: Communication is not ready.
1: Communication is ready.
RECSTS Receive Status Flag
0: Bus idle, in transmission or bus off state
1: In reception
TRMSTS Transmit Status Flag
0: Bus idle or in reception
1: In transmission or bus off state
BOSTS Bus Off Status Flag
0: Not in bus off state
1: In bus off state
EPSTS Error Passive Status Flag
0: Not in error passive state
1: In error passive state
CSLPSTS Channel Stop Status Flag
0: Not in channel stop mode
1: In channel stop mode
CHLTSTS Channel Halt Status Flag
0: Not in channel halt mode
1: In channel halt mode
CRSTSTS Channel Reset Status Flag
0: Not in channel reset mode
1: In channel reset mode
24 23 22 21
0 0 0 0
R R R R
8 7 6 5
COMST RECST TRMST
—
S S S
0 0 0 0
R R R R
21. CAN Interface
20 19 18 17
REC[7:0]
0 0 0 0
R R R R
4 3 2 1
CSLPST CHLTST
BOSTS EPSTS
S S
0 0 1 0
R R R R
16
0
R
0
CRSTS
TS
1
R
21-26