Ssl Delay Register (Ssldr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.2

SSL Delay Register (SSLDR)

SSLDR is a 32-bit register that adjusts the timing between the SPBSSL signal and the SPBCLK signal.
The settings of this register are reflected both in external address space read mode and SPI operating mode.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value:
0
R/W:
R
Bit Bit Name
31 to 19 ―
18 to 16 SPNDL[2:0]
15 to 11 ―
10 to 8 SLNDL[2:0]
7 to 3 ―
2 to 0 SCKDL[2:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - -
0 0 0 0 1
R R R R R/W
Initial
Value R/W
All 0 R
111 R/W
All 0 R
111 R/W
All 0 R
111 R/W
25 24 23 22
- - - -
0 0 0 0
R R R R
9 8 7 6
SLNDL[2:0] - -
1 1 0 0
R/W R/W R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Next Access Delay
Sets the period from transfer end to next transfer start (next access).
000: 1 SPBCLK cycle
001: 2 SPBCLK cycles
010: 3 SPBCLK cycles
011: 4 SPBCLK cycles
100: 5 SPBCLK cycles
101: 6 SPBCLK cycles
110: 7 SPBCLK cycles
111: 8 SPBCLK cycles
Reserved
These bits are always read as 0. The write value should always be 0.
SPBSSL Negation Delay
Sets the period from the time the last SPBCLK edge is sent of a transfer
to SPBSSL pin negation (SPBSSL negation delay).
000: 1.5 SPBCLK cycles
001: 2.5 SPBCLK cycles
010: 3.5 SPBCLK cycles
011: 4.5 SPBCLK cycles
100: 5.5 SPBCLK cycles
101: 6.5 SPBCLK cycles
110: 7.5 SPBCLK cycles
111: 8.5 SPBCLK cycles
Reserved
These bits are always read as 0. The write value should always be 0.
Clock Delay
Sets the period from SPBSSL pin assertion to SPBCLK oscillation (clock
delay).
000: 1 SPBCLK cycle
001: 2 SPBCLK cycles
010: 3 SPBCLK cycles
011: 4 SPBCLK cycles
100: 5 SPBCLK cycles
101: 6 SPBCLK cycles
110: 7 SPBCLK cycles
111: 8 SPBCLK cycles
17. SPI Multi I/O Bus Controller
21 20 19 18 17
- - - SPNDL[2:0]
0 0 0 1 1
R R R R/W R/W
5 4 3 2 1
- - - SCKDL[2:0]
0 0 0 1 1
R R R R/W R/W
16
1
R/W
0
1
R/W
17-8