Rscan0Gaflp1J - Receive Rule Pointer 1 Register (J = 0 To 15) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.16 RSCAN0GAFLP1j — Receive Rule Pointer 1 Register (j = 0 to 15)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 050C
Initial value: 0000 0000
H
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— —
0 0 0
Initial value
R/W R R R/W
Table 21.30
Bit Position
31 to 14
13 to 0
Modify the RSCAN0GAFLP1j register when the AFLDAE bit in the RSCAN0GAFLECTR register is
set to 1 (receive rule table write is enabled) in global reset mode.
GAFLFDP [13:0] Bits
These bits are used to specify FIFO buffers that store receive messages that have passed through the
filter. Up to eight FIFO buffers are selectable. However, when the GAFLRMV bit in the
RSCAN0GAFLP0j register is set to 1 (a message is stored in the receive buffer), up to seven FIFO
buffers can be selected.
Only receive FIFO buffers and the transmit/receive FIFO buffer for which the CFM[1:0] bits in the
RSCAN0CFCCk register are set to 00
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (j * 0010 )
H H
28 27 26 25
— — — —
0 0 0 0
R R R R
12 11 10 9
0 0 0 0
R/W R/W R/W R/W
RSCAN0GAFLP1j register contents
Bit Name Function
Reserved These bits are always read as 0. The write value should always be 0.
GAFLFDP [13:0] FIFO Buffer z Select (z = 0 to 13)
z = 0 to 7
0: Receive FIFO buffer z is not selected.
1: Receiver FIFO buffer z is selected.
z = 8 to 13
0: Transmit/receive FIFO buffer z-8 is not selected.
1: Transmit/receive FIFO buffer z-8 is selected.
B
24 23 22 21
— — — —
0 0 0 0
R R R R
8 7 6 5
GAFLFDP [13:0]
0 0 0 0
R/W R/W R/W R/W
(receive mode) or 10 (gateway mode) are selectable.
B
21. CAN Interface
20 19 18 17
— — — —
0 0 0 0
R R R R
4 3 2 1
0 0 0 0
R/W R/W R/W R/W
16
—
0
R
0
0
R/W
21-50