Spi Mode Write Data Register 0 (Smwdr0); Spi Mode Write Data Register 1 (Smwdr1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.16

SPI Mode Write Data Register 0 (SMWDR0)

SMWDR0 is a 32-bit register that sets the write data in SPI operating mode.
Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the
SPI mode enable setting register (SMENR). Be sure to access from address 0.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit: 31
Initial value: 0
R/W: R/W
Bit: 15
Initial value: 0
R/W: R/W
Bit Bit Name
31 to 0 WDATA0
[31:0]
17.4.17

SPI Mode Write Data Register 1 (SMWDR1)

SMWDR1 is a 32-bit register that sets the write data in SPI operating mode.
This register is enabled when the BSZ[1:0] bits in CMNCR are set to 01 (two serial flash memories connected) and
disabled when the BSZ[1:0] bits in CMNCR are set to 00 (one serial flash memory connected).
Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the
SPI mode enable setting register (SMENR). Be sure to access from address 0.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit: 31
Initial value: 0
R/W: R/W
Bit: 15
Initial value: 0
R/W: R/W
Bit Bit Name
31 to 0 WDATA1
[31:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
0 0 0 0 0
R/W R/W R/W R/W R/W
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
Initial
Value R/W
All 0 R/W
30 29 28 27 26
0 0 0 0 0
R/W R/W R/W R/W R/W
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
Initial
Value R/W
All 0 R/W
25 24 23 22 21
WDATA0[31:16]
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
WDATA0[15:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
Description
Write Data
Holds the data to be written in SPI operating mode.
Data bits differ depending on the settings of SFDE and BSZ[1:0] bits in
CMNCR and SPIDE[3:0] bits in SMENR.
BSZ[1:0] = 01, SPIDE[3:0] = 1111, SFDE = 1: Write data[63:32].
BSZ[1:0] = 01, SPIDE[3:0] = 1111, SFDE = 0: Write data[31:0].
Other than the above: Write data[31:0].
25 24 23 22 21
WDATA1[31:16]
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
WDATA1[15:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
Description
Write Data
Holds the data to be written in SPI operating mode.
Data bits differ depending on the settings of SFDE and BSZ[1:0] bits in
CMNCR and SPIDE[3:0] bits in SMENR.
BSZ[1:0] = 01, SPIDE[3:0] = 1111, SFDE = 1: Write data[31:0].
BSZ[1:0] = 01, SPIDE[3:0] = 1111, SFDE = 0: Write data[63:32].
Other than the above: Bits in this register are disabled.
17. SPI Multi I/O Bus Controller
20 19 18 17 16
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
20 19 18 17 16
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
17-23