Facility For Delaying Sda Output - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.7

Facility for Delaying SDA Output

The RIIC module incorporates a facility for delaying output on the SDA line. The delay can be applied
to all output (issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals) on
the SDA line.
With the SDA output delay facility, SDA output is delayed from detection of a falling edge of the SCL
signal to ensure that the SDA signal is output within the interval over which the SCL (clock) signal is at
the low level. Doing this leads to usage with the aim of preventing erroneous operation of
communications devices, with the aim of satisfying the 300-ns (min.) data-hold time requirement of the
SMBus specification.
The output delay facility is enabled by setting the RIICnMR2.SDDL[2:0] bits to any value other than
000 , and disabled by setting the same bits to 000
B
While the SDA output delay facility is enabled (i.e. while the SDDL[2:0] bits in IMCR2 are set to any
value other than 000
output delay counter as the internal base clock (IICφ) for the RIIC module or as a clock signal derived
by dividing the frequency of the internal base clock by two (IICφ/2). The counter counts the number of
cycles set in the SDDL[2:0] bits in IMCR2. After counting of the set number of cycles of delay is
completed, the RIIC module places the required output (start, restart, or stop condition, data, or an
ACK or NACK signal) on the SDA line.
[Transmit mode]
SCLn
SDAn
[Receive mode]
SCLn
SDAn
[When a condition is issued]
SCLn
SDAn
BBSY
ST
Figure 18.22
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
), the RIICnMR2.DLCS bit selects the clock source for counting by the SDA
B
P0φ sampling error (1 P0φ (max))
Digital noise filter delay time (NFE, NF[1:0] settings = 0.5 P0φ (min), 1 IICφ to 4 IICφ (max))
SDA output delay time (DLCS,SDDL[2:0] settings = 0 (min) to 14 IICφ (max))
S
1 to 7
b7 to b1
SDA output delay
RIICn RIICn RIICn RIICn
BRH BRL BRH BRL
S 1
b7
1
*
SDA Output Delay Facility
.
B
b7 to b1
SDA output delay
8
b0
RIICn
BRL
2 to 8 9
b6 to b0 ACK/NACK
SDA output delay
Note 1. The output is delayed by the number of cycles set by the SDDL[2:0] bits when a start
(S), restart (Sr), or stop (P) condition is issued.
18. I²C Bus Interface
SDA output release timing
8
b0 ACK/NACK
SDA output release timing
9
ACK/NACK
RIICn RIICn RIICn
BRH BRL BRH
1 to 9
Sr
1
*
9
P
RIICn
BRL
P
1
*
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