Smbus Host Notification Protocol/Notify Arp Master - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
For the ACK receive timing (rising edge of the ninth SMBCLK clock cycle), monitor theRIICnSR2.
TEND flag in master transmit mode (master transmitter) and the RIICnSR2.RDRF flag in master
receive mode (master receiver). For this reason, perform bytewise transmit operation in master transmit
mode, and hold the RIICnMR3.RDRFS bit 0 until the byte just before reception of the final byte in
master receive mode. While the RDRFS bit is 0, the RDRF flag is set to 1 at the rising edge of the ninth
SMBCLK clock cycle.
If the period measured with the internal timer exceeds the total clock low-level extended period [master
device] T
clock low-level detection timeout T
must stop the transaction by issuing a stop condition. In master transmit mode, immediately stop the
transmit operation (writing data to RIICnDRT).
SCLn
SDAn
BBSY
TDRE
TEND
RDRF
RDRFS
START
STOP
Figure 18.41
18.14.2

SMBus Host Notification Protocol/Notify ARP Master

In communications over an SMBus, a slave device can temporarily act as a master device to notify the
SMBus host (or ARP master) of (or request the SMBus host for) its own slave address or to request its
own slave address from the SMBus host.
For this LSI to operate as an SMBus host (or ARP master), the host address (0001 000
slave device must be detected as a slave address, so the RIIC has a function for detecting the host
address. To detect the host address as a slave address, set the RIICnMR3.SMBS bit and the
RIICnSER.HOAE bit to 1. Operation after the host address has been detected is the same as normal
slave operation.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
: 10 ms (max.) of the SMBus standard or the total of measured periods exceeds the
LOW:MEXT
Start
T
LOW:MEXT
S 1 2 7 8
7-bit slave address R/W
SMBus Timeout Measurement
: 25 ms (min.) of the SMBus standard, the master device
TIMEOUT
SMBus standard T
LOW:SEXT
T
LOW:MEXT
T
LOW:SEXT
Clk Clk
ACK ACK
T
LOW:MEXT
9 1 2 2 7 7 8 8 9
ACK Data ACK
Measured with the interval timer
18. I²C Bus Interface
: Total clock low-level extended period (slave device)
: Total clock low-level extended period (master device)
Clk
ACK
T T
LOW:MEXT LOW:MEXT
1 2 2 7 7 8 8 9
Data
A/NA
) sent from the
B
Stop
P
18-89