Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.6

Register

Table 23.3 shows the register configuration.
Table 23.3 Register Configuration
Channel Register Name
0 Transmitter channel 1 audio register
(Transmit)
Transmitter channel 2 audio register
Transmitter channel 1 status register
Transmitter channel 2 status register
Transmitter user data register
1 Receiver channel 1 audio register
(Receive)
Receiver channel 2 audio register
Receiver channel 1 status register
Receiver channel 2 status register
Receiver user data register
0, 1 (Common) Control register
Status register
0, 1 (Common) Transmitter DMA audio data register
Receiver DMA audio data register
Note: All registers are longword registers and must be accessed as such.
A register diagram containing a 0 indicates that the write value should always be 0 (if the register is writeable) and that
the read value should always be 0 (if readable).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Abbreviation Address
TLCA H'FFFF D800
TRCA H'FFFF D804
TLCS H'FFFF D808
TRCS H'FFFF D80C
TUI H'FFFF D810
RLCA H'FFFF D814
RRCA H'FFFF D818
RLCS H'FFFF D81C
RRCS H'FFFF D820
RUI H'FFFF D824
CTRL H'FFFF D828
STAT H'FFFF D82C
TDAD H'FFFF D830
RDAD H'FFFF D834
23. Renesas SPDIF Interface
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
23-5