21.11 Notes On The Rs-Can Module - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

21.11 Notes on the RS-CAN Module

• When changing a global mode, check the GSLPSTS, GHLTSTS, and GRSTSTS flags in the
RSCAN0GSTS register for transitions. When changing a channel mode, check the CSLPSTS,
CHLTSTS, and CRSTSTS flags in the RSCAN0CmSTS register (m = 0 or 1) for transitions.
• The acceptance filter processing checks receive rules sequentially in ascending order from the
minimum rule number. If the same ID, IDE bit, or RTR bit value is set for multiple receive rules,
the minimum number of receive rule is used for the acceptance filter processing. If the message
does not pass through the subsequent DLC filter processing, the data processing is terminated
without returning to the acceptance filter processing and the message is not stored in the buffer.
• When linking transmit buffers to transmit/receive FIFO buffers or allocating transmit buffers to
transmit queues, set the control register (RSCAN0TMCp) of the corresponding transmit buffer to
00
used. Flags in other status registers (registers RSCAN0TMTRSTS0, RSCAN0TMTARSTS0,
RSCAN0TMTCSTS0, and RSCAN0TMTASTS0), which correspond to transmit buffers linked to
transmit/receive FIFO buffers or allocated to transmit queues remain unchanged. Set the enable
bit in the corresponding interrupt enable register (the RSCAN0TMIEC0 register) to 0 (transmit
buffer interrupt is disabled).
• Transmit buffers that are linked to transmit/receive FIFO buffers must not bet allocated to transmit
queues.
• Only a single transmit/receive FIFO buffer can be linked to a transmit buffer. Do not link two or
more transmit/receive FIFO buffers to transmit buffers of the same number.
• When the CANm bit time clock is selected as a timestamp counter clock source, the timestamp
counter stops when the corresponding channel has transitioned to channel reset mode or channel
halt mode.
• In case of an attempt to store a new received message when the receive FIFO buffer and the
transmit/receive FIFO buffer are full, the new message is discarded. If you wish to store a new
transmit message in the transmit/receive FIFO buffer or the transmit queue, check that the
transmit/receive FIFO buffer or the transmit queue is not full.
• The values of unused receive buffer registers (RSCAN0RMIDq, RSCAN0RMPTRq,
RSCAN0RMDF0q, and RSCAN0RMDF1q registers), receive FIFO buffer access registers
(RSCAN0RFIDx, RSCAN0RFPTRx, RSCAN0RFDF0x, and RSCAN0RFDF1x registers), and
transmit/receive FIFO buffer access registers (RSCAN0CFIDk, RSCAN0CFPTRk,
RSCAN0CFDF0k, and RSCAN0CFDF1k registers) are undefined when the RS-CAN module
transitions to global operation mode or global test mode after exiting from global reset mode.
R01UH0437EJ0600 Rev.6.00
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. The status register (RSCAN0TMSTSp) of the corresponding transmit buffer should not be
H
21. CAN Interface
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