Serial Data Reception (Clock Synchronous Mode) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.5.5

Serial Data Reception (Clock Synchronous Mode)

Figure 15.21 and Figure 15.22 show examples of SCI operation for serial reception in clock synchronous mode.
In serial data reception, the SCI operates as described below.
1. The value of the RE bit in SCR becoming 1 places the signal output on the RTS pin at the low level (when the RTS
function is in use).
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
input or output, and stores the receive data in RSR.
3. If an overrun error occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is 1 at this time, an ERI interrupt
request is generated. Receive data is not transferred to RDR.
4. When reception finishes successfully, receive data is transferred to RDR. If the RIE bit in SCR is 1 at this time, an
RXI interrupt request is generated. Continuous reception is enabled by reading the receive data transferred to RDR
in this RXI interrupt processing routine before reception of the next receive data is completed. Reading out the
received data that have been transferred to RDR causes the RTSn# pin to output the low level (when the RTS
function is in use).
Synchronization
clock
Serial data
RXI interrupt flag
SSR.ORER flag
RXI interrupt
request
generated
Figure 15.21 Example of Operation for Serial Reception in Clock Synchronous Mode (1) (when RTS Function is
not Used)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit 7 Bit 0
RDR data read in RXI
interrupt processing routine
1 frame
15. Serial Communications Interface
Bit 7 Bit 0 Bit 1
RXI interrupt
request
generated
Bit 6 Bit 7
ERI interrupt request
generated by overrun error
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