Axi Bus Response Error Clear Register 2 (Axirerrclr2) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.12

AXI Bus Response Error Clear Register 2 (AXIRERRCLR2)

This register clears the AXI bus response error status.
Bit: 31
—
Initial value:
0
R/W:
R
Bit: 15
—
Initial value:
0
R/W:
R
Bit Bit Name
31 —
30 VDC501
RRESP
CLR
29 —
28 VDC501
BRESP
CLR
27 —
26 VDC502
RRESP
CLR
25 to 19 —
18 VDC504
RRESP
CLR
17 to 0 —
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
VDC501 VDC501 VDC502
— —
RRESP BRESP RRESP
CLR CLR CLR
0 0 0 0 0
R/W R R/W R R/W
14 13 12 11 10
— — — — —
0 0 0 0 0
R R R R R
Initial
Value R/W Description
0 R Reserved
This bit is always read as 0. The write value should always be 0.
0 R/W VDC501RRESP[1:0] Clear
Writing 1 to this bit clears the VDC501RRESP[1:0] bits to 00.
This bit is always read as 0.
0 R Reserved
This bit is always read as 0. The write value should always be 0.
0 R/W VDC501BRESP[1:0] Clear
Writing 1 to this bit clears the VDC501BRESP[1:0] bits to 00.
This bit is always read as 0.
0 R Reserved
This bit is always read as 0. The write value should always be 0.
0 R/W VDC502RRESP[1:0] Clear
Writing 1 to this bit clears the VDC502RRESP[1:0] bits to 00.
This bit is always read as 0.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W VDC504RRESP[1:0] Clear
Writing 1 to this bit clears the VDC504RRESP[1:0] bits to 00.
This bit is always read as 0.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
25 24 23 22 21
— — — — —
0 0 0 0 0
R R R R R
9 8 7 6 5
—
— — — —
0 0 0 0 0
R R R R R
5. LSI Internal Bus
20 19 18 17 16
VDC504
— — — —
RRESP
CLR
0 0 0 0 0
R R R/W R R
4 3 2 1 0
—
— — — —
0 0 0 0 0
R R R R R
5-25