Rscan0Cfrists - Transmit/Receive Fifo Buffer Receive Interrupt Flag Status Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.41 RSCAN0CFRISTS — Transmit/receive FIFO buffer Receive Interrupt Flag
Status Register
Access: Can be read in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0248
Initial value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.55
Bit Position
31 to 6
5
4
3
2
1
0
The RSCAN0CFRISTS register is cleared to 0000 0000
CFkRXIF Flag (k = 0 to 5)
The CFkRXIF flag is set to 1 when the CFRXIF flag in the RSCAN0CFSTSk register is set to 1 (a
transmit/receive FIFO receive interrupt request is present). When the CFRXIF flag is cleared to 0, the
CFkRXIF flag is cleared to 0.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RSCAN0CFRISTS register contents
Bit Name Function
Reserved These bits are always read as 0.
CF5RXIF Transmit/Receive FIFO Buffer Receive Interrupt Request Status Flag
CF4RXIF
CF3RXIF (k = 0 to 5)
CF2RXIF
CF1RXIF
CF0RXIF
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — — —
0 0 0 0
R R R R
0: No transmit/receive FIFO buffer k receive interrupt request is present.
1: A transmit/receive FIFO buffer k receive interrupt request is present.
in global reset mode.
H
21. CAN Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
CF5RXI CF4RXI CF3RXI CF2RXI
F F F F
0 0 0 0
R R R R
17 16
— —
0 0
R R
1 0
CF1RXI CF0RXI
F F
0 0
R R
21-85