Rscan0Gaflcfg0 - Receive Rule Configuration Register 0 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.12 RSCAN0GAFLCFG0 — Receive Rule Configuration Register 0
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 009C
Initial value: 0000 0000
H
Bit 31 30 29
Initial value 0 0 0
R/W R/W R/W R/W
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.26
Bit Position
31 to 24
23 to 16
15 to 0
Modify the RSCAN0GAFLCFG0 register only in global reset mode.
Up to 64 x (number of channels) rules can be registered in the receive rule table as the entire unit. The
number of receive rules per channel should meet the following conditions.
• The maximum number of rules per channel is 128.
• The total of the number of rules allocated to each channel is not larger than the number of rules
that can be registered in the entire unit.
RNC0[7:0] Bits
These bits are used to set the number of rules to be registered in the channel 0 receive rule table.
Set these bits to a value within the range of 00
RNC1[7:0] Bits
These bits are used to set the number of rules to be registered in the channel 1 receive rule table.
Set these bits to a value within the range of 00
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
28 27 26 25
RNC0[7:0]
0 0 0 0
R/W R/W R/W R/W
12 11 10 9
— — — —
0 0 0 0
R R R R
RSCAN0GAFLCFG0 register contents
Bit Name Function
RNC0[7:0] Number of Rules for Channel 0
Set the number of receive rules exclusively used for channel 0.
RNC1[7:0] Number of Rules for Channel 1
Set the number of receive rules exclusively used for channel 1.
Reserved These bits are always read as 0. The write value should always be 0.
24 23 22 21
0 0 0 0
R/W R/W R/W R/W
8 7 6 5
— — — —
0 0 0 0
R R R R
to 80 .
H H
to 80 .
H H
21. CAN Interface
20 19 18 17
RNC1[7:0]
0 0 0 0
R/W R/W R/W R/W
4 3 2 1
— — — —
0 0 0 0
R R R R
16
0
R/W
0
—
0
R
21-44