Setting Example 3 (Register Mode/Continuous Execution) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.8.3

Setting Example 3 (Register Mode/Continuous Execution)

The following table shows a setting example applicable when DMA transfer is executed using the settings shown below.
Table 9.24 DMA Transfer Setting Example 3
Item
Channel used
Priority control
DMA mode
Transfer mode
Register set used
Next0
Start address
Address direction
Data size
DMA transfer byte count 512 bytes
Next1
Start address
Address direction
Data size
DMA transfer byte count 2048 bytes
DMA transfer request
DMAACK signal
DMA transfer end interrupt mask
CACHE setting
Setting example 3
DCTRL = 0000_0001H (DMA setting)
N0SA = 1111_0000H (source address)
N0DA = 3333_0000H (destination address)
N0TB = 0000_0200H (transfer byte count)
N1SA = 2222_0000H (source address)
N1DA = 4444_0000H (destination address)
N1TB = 0000_0800H (transfer byte count)
CHCFG = 6176_2001H (configuration)
CHITVL = 0000_0000H (interval)
CHEXT = 0000_0000H (CACHE setting)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Description
1
Round robin
Register
Block transfer
Use Next0 and then Next1 continuously
Source
1111_0000H
Fixed
32 bits
Source
2222_0000H
Fixed
32 bits
Auto request
Not output
Mask the DMA transfer end interrupt upon completion of Next0
Default value
9. Direct Memory Access Controller
Destination
3333_0000H
Fixed
512 bits
Destination
4444_0000H
Fixed
512 bits
9-70