Fc Mode Register (Ssifcmr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.3.11

FC Mode Register (SSIFCMR)

SSIFCMR sets the maximum and minimum allowable numbers of cycles of the peripheral clock 1 (P1φ) for each SSIWS
cycle, when frequency change detection is enabled.
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value: 0
R/W:
R
Bit Bit Name
31, 30 ―
29 to 16 MAXV
15, 14 ―
13 to 0 MINV
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
-
0 0 0 0 0
R R/W R/W R/W R/W
14 13 12 11 10
-
0 0 0 0 0
R R/W R/W R/W R/W
Initial
Value R/W
All 0 R
0 R/W
All 0 R
0 R/W
25 24 23 22 21
MAXV
0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6
MINV
0 0 0 0
R/W R/W R/W R/W R/W
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Maximum Value
Sets the maximum allowable number of cycles of the peripheral clock 1
(P1φ) for each SSIWS cycle, when SSIFCCR.FCEN = 1.
Reserved
These bits are always read as 0. The write value should always be 0.
Minimum Value
Sets the minimum allowable number of cycles of the peripheral clock 1
(P1φ) for each SSIWS cycle, when SSIFCCR.FCEN = 1.
19. Serial Sound Interface
20 19 18 17
0 0 0 0 0
R/W R/W R/W R/W
5 4 3 2 1
0 0 0 0 0
R/W R/W R/W R/W
16
0
R/W
0
0
R/W
19-20