Using Interval Timer Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
WTCNT
value
H'FF
H'00
WDTOVF
signal
Internal
reset signal*
[Legend]
WT/IT: Timer mode select bit
TME: Timer enable bit
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 12.4 Operation in Watchdog Timer Mode
12.4.3

Using Interval Timer Mode

When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This
enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in WTCSR, and set the initial
value of the counter in WTCNT.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, this module sets the IOVF bit in WTCSR to 1 and an interval timer interrupt request is
sent to the interrupt controller. The counter then resumes counting.
WTCNT value
H'FF
H'00
WT/IT = 0
TME = 1
[Legend]
ITI: Interval timer interrupt request generation
Figure 12.5 Operation in Interval Timer Mode
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H'00 written
WT/IT = 1
in WTCNT
TME = 1
Overflow
ITI
Overflow
WOVF = 1
WDTOVF and internal reset generated
64 × P0φ clock cycles
128 × P0φ clock cycles
Overflow Overflow
ITI ITI
12. Watchdog Timer
Time
H'00 written
in WTCNT
Overflow
Time
ITI
12-9