Receive Shift Register (Scrsr); Receive Fifo Data Register (Scfrdr) - Renesas RZ/A Series User Manual

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Table of Contents

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Serial mode register_4

Bit rate register_4

Serial control register_4

Transmit FIFO data register_4

Serial status register_4

Receive FIFO data register_4

FIFO control register_4

FIFO data count set register_4

Serial port register_4

Line status register_4

Serial extension mode register_4

Note 1. Only 0 can be written to clear the flag. Bits 15 to 8, 3, and 2 are read-only bits that cannot be modified.

Note 2. Only 0 can be written to clear the flag. Bits 15 to 1 are read-only bits that cannot be modified.

Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first,

being converted to parallel form. When one byte has been received, it is automatically transferred to the receive FIFO

data register (SCFRDR).

The CPU cannot read from or write to SCRSR directly.

SCFRDR is a 16-stage FIFO register that stores serial receive data. The reception of one byte of serial data is complete

when the received data is moved from the receive shift register (SCRSR) to SCFRDR for storage. Continuous reception

is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive

data in the SCFRDR, the value is undefined.

When SCFRDR is full of receive data, subsequent serial data is lost.

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

Abbreviation

Initial value:

Initial value:

14. Serial Communication Interface with FIFO

Initial Value

Rz/a1 series Rz/a1lu series Rz/a1lc series