Riicnmr1 - I²C Bus Mode Register 1 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.3 RIICnMR1 — I²C Bus Mode Register 1
Access: RIICnMR1 is a 32-bit readable/writable register.
RIICnMR1L and RIICnMR1H are 16-bit readable/writable registers.
RIICnMR1LL, RIICnMR1LH, RIICnMR1HL, and RIICnMR1HH are 8-bit readable/writable registers.
Address: RIICnMR1: <RIICn_base> + 0008
RIICnMR1L: <RIICn_base> + 0008
RIICnMR1LL: <RIICn_base> + 0008
RIICnMR1HH: <RIICn_base> + 000B
Initial Value: 0000 0008
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 18.8
Bit Position
31 to 7
6 to 4
3
2 to 0
Note 1.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnMR1H: <RIICn_base> + 000A
H
, RIICnMR1LH: <RIICn_base> + 0009
H
H
This register is initialized by any reset.
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RIICnMR1 register contents
Bit Name Function
― Reserved
These bits are read as 0. The write value should be 0.
Internal Reference Clock (IIC φ ) Selection
CKS[2:0]
b6 b4
0 0 0: IIC φ = P0 φ /1
0 0 1: IIC φ = P0 φ /2
0 1 0: IIC φ = P0 φ /4
0 1 1: IIC φ = P0 φ /8
1 0 0: IIC φ = P0 φ /16
1 0 1: IIC φ = P0 φ /32
1 1 0: IIC φ = P0 φ /64
1 1 1: IIC φ = P0 φ /128
*1
BCWP BC Write Protect
0: Enables a value to be written in the BC[2:0] bits.
BC[2:0] Bit Counter
b2 b0
0 0 0: 9 bits
0 0 1: 2 bits
0 1 0: 3 bits
0 1 1: 4 bits
1 0 0: 5 bits
1 0 1: 6 bits
1 1 0: 7 bits
1 1 1: 8 bits
When rewriting the BC[2:0] bits, write 0 to the BCWP bit simultaneously.
H
, RIICnMR1HL: <RIICn_base> + 000A
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — — CKS[2:0]
0 0 0 0
R R R R/W
(This bit is read as 1.)
18. I²C Bus Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
BCWP
0 0 1 0
R/W R/W R/W R/W
,
H
17 16
— —
0 0
R R
1 0
BC[2:0]
0 0
R/W R/W
18-14