Csn Space Bus Control Register (Csnbcr) (N = 0 To 5) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0 to 5)

CSnBCR is a 32-bit readable/writable register that specifies the memory connected to each space, the number of idle
cycles between bus cycles, and the bus width.
Do not access external memory for the corresponding area until CSnBCR initial setting and pin setting are completed.
Idle cycles may be inserted even when they are not specified. For details, see section 8.5.10, Wait between Access
Cycles.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
Note: * B'10 in boot mode 0; B'11 in boot modes 1 to 3.
Bit Bit Name
31 ―
30 to 28 IWW[2:0]
27 to 25 IWRWD[2:0]
24 to 22 IWRWS[2:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
IWW[2:0] IWRWD[2:0]
0 1 1 0 1
R/W R/W R/W R/W R/W
14 13 12 11 10
TYPE[2:0] - BSZ[1:0]
0 0 0 1 1*
R/W R/W R/W R R/W
Initial
Value R/W
0 R
011 R/W
011 R/W
011 R/W
25 24 23 22 21
IWRWS[2:0]
1 0 1 1 0
R/W R/W R/W R/W R/W
9 8 7 6 5
- - - -
0* 0 0 0 0
R/W R R R R
Description
Reserved
This bit is always read as 0. The write value should always be 0.
Idle Cycles between Write-Read Cycles and Write-Write Cycles
These bits specify the number of idle cycles to be inserted after the access
to a memory that is connected to the space. The target access cycles are
the write-read cycle and write-write cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Idle Cycles for Another Space Read-Write
Specify the number of idle cycles to be inserted after the access to a
memory that is connected to the space. The target access cycle is a read-
write one in which continuous access cycles switch between different
spaces.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Idle Cycles for Read-Write in the Same Space
Specify the number of idle cycles to be inserted after the access to a
memory that is connected to the space. The target cycle is a read-write
cycle of which continuous access cycles are for the same space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
8. Bus State Controller
20 19 18 17 16
IWRRD[2:0] IWRRS[2:0]
1 1 0 1
R/W R/W R/W R/W R/W
4 3 2 1
- - - -
0 0 0 0
R R R R
1
0
-
0
R
8-8