Operation; Access Size And Data Alignment - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.5

Operation

8.5.1

Access Size and Data Alignment

This LSI supports little endian, in which the least significant byte (LSB) is that in the direction of the 0th address.
Data bus width can be selected from 8 bits, 16 bits, and 32 bits for the normal memory and SRAM with byte selection.
Data bus width can be selected from 16 bits and 32 bits for SDRAM. For MPX-I/O, the data bus width is fixed to either
8 or 16 bits, or made selectable as 8 bits or 16 bits by one of the address lines.
Data bus width varies depending on boot mode. For details, refer to section 8.3.2, Data Bus Width and Related Pin
Setting for Each Area Depending on Boot Mode.
Data alignment is performed in accordance with the data bus width selected for the device. This also means that four read
operations are required to read 32-bit data from a byte-width device. In this LSI, data alignment and conversion of data
length is performed automatically between the respective interfaces.
Table 8.5 to Table 8.7 show the relationship between device data width and access unit.
Table 8.5 32-Bit External Device Access and Data Alignment in Little Endian
Operation
8-bit access at address 0
8-bit access at address 1
8-bit access at address 2
8-bit access at address 3
16-bit access at address 0
16-bit access at address 2
32-bit access at address 0
Table 8.6 16-Bit External Device Access and Data Alignment in Little Endian
Operation
8-bit access at address 0
8-bit access at address 1
8-bit access at address 2
8-bit access at address 3
16-bit access at address 0
16-bit access at address 2
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Data Bus
D31 to D23 to D15 to
D24 D16 D8
― ― ―
― ― Data 7 to
0
― Data 7 to ―
0
Data 7 to ― ―
0
― ― Data 15 to
8
Data 15 to Data 7 to ―
8 0
Data 31 to Data 23 to Data 15 to
24 16 8
Data Bus
D31 to D23 to D15 to
D24 D16 D8
― ― ―
― ― Data 7 to
0
― ― ―
― ― Data 7 to
0
― ― Data 15 to
8
― ― Data 15 to
8
Strobe Signals
WE3, WE2,
D7 to D0 DQMUU DQMUL
Data 7 to ― ―
0
― ― ―
― ― Assert
― Assert ―
Data 7 to ― ―
0
― Assert Assert
Data 7 to Assert Assert
0
Strobe Signals
WE3, WE2,
D7 to D0 DQMUU DQMUL
Data 7 to ― ―
0
― ― ―
Data 7 to ― ―
0
― ― ―
Data 7 to ― ―
0
Data 7 to ― ―
0
8. Bus State Controller
WE1, WE0,
DQMLU DQMLL
― Assert
Assert ―
― ―
― ―
Assert Assert
― ―
Assert Assert
WE1, WE0,
DQMLU DQMLL
― Assert
Assert ―
― Assert
Assert ―
Assert Assert
Assert Assert
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