Data Control Register (Spdcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
Table 16.3 Relationship between SPBR and BRDV1 and BRDV0 Settings
SPBR (n) BRDV[1:0] (N)
0 0
1 0
2 0
3 0
4 0
5 0
5 1
5 2
5 3
255 3
Note 1. Examine the timing specifications to determine the bit rate in the actual system.
16.3.9

Data Control Register (SPDCR)

SPDCR selects the width to access SPDR from longword-, word-, and byte-width, and enables or disables dummy data
transmission for the master mode operation.
If the contents of SPDCR are changed while bit TEND in the status register (SPSR) indicates that transmission is not
completed, the subsequent operation cannot be guaranteed.
Bit Bit Name
7 TXDMY
6 SPLW1
5 SPLW0
4 to 0 ―
Note: * The data length is specified by the SPB3 to SPB0 bits in the command register (SPCMD).
See section 16.3.5, Data Register (SPDR).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Division Ratio P1φ = 50 MHz
1
2 * 25.00 Mbps
4 12.50 Mbps
6 8.33 Mbps
8 6.25 Mbps
10 5.00 Mbps
12 4.17 Mbps
24 2.08 Mbps
48 1.04 Mbps
96 520.83 Kbps
4096 12.21 Kbps
Bit: 7 6 5
TXDMY SPLW1 SPLW0
Initial value: 0 0 1
R/W: R/W R/W R/W
Initial Value R/W Function
0 R/W Dummy Data Transmission Enable
Enables or disables dummy data transmission.
When communication is performed with this bit set to 1, dummy data is
transmitted from the MOSI pin and a serial communication can be
performed even if there is no transmit data in the transmit buffer.
Specifically, if there is no transmit data in the transmit buffer and this bit is
set to 1, dummy data is transferred to the shift register. Data previously
transmitted from the pin is used as dummy data. If this bit is set to 1 after
the initialization and a transfer is performed, the transmitted dummy data
is undefined.
0: Disables dummy data transmission.
1: Enables dummy data transmission.
Note: This bit is valid only in the master mode.
0 R/W Access Width Specification
1 R/W Specifies the width for accessing the data register (SPDR). If the length of
data transferred to SPDR does not agree with these bit settings,
operation is not guaranteed.*
00: Setting prohibited
01: SPDR is accessed in bytes (8 bits).
10: SPDR is accessed in words (16 bits).
11: SPDR is accessed in longwords (32 bits).
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
16. Renesas Serial Peripheral Interface
Bit Rate
P1φ = 64 MHz
32.00 Mbps
16.00 Mbps
10.67 Mbps
8.00 Mbps
6.40 Mbps
5.33 Mbps
2.67 Mbps
1.33 Mbps
666.67 Kbps
15.63 Kbps
4 3 2 1 0
⎯ ⎯ ⎯ ⎯ ⎯
0 0 0 0 0
R R R R R
P1φ = 66.67 MHz
33.33 Mbps
16.67 Mbps
11.11 Mbps
8.33 Mbps
6.67 Mbps
5.56 Mbps
2.78 Mbps
1.39 Mbps
694.44 Kbps
16.28 Kbps
16-12