Clock; Cts And Rts Functions - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be

selected as the SCI's transfer clock, according to the setting of the CM bit in SMR and the CKE[1:0] bits in SCR.

When an external clock is input to the SCKn pin, the clock frequency should be 16 times the bit rate (when ABCS in

SEMR = 0) and 8 times the bit rate (when ABCS in SEMR = 1).

When the SCI is operated on an internal clock, the clock can be output from the SCKn pin. The frequency of the clock

output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the

transmit data, as shown in Figure 15.4.

Phase Relationship between Output Clock and Transmit Data

(Asynchronous Mode: SMR.CHR = 0, PE = 1, MP = 0, STOP = 1)

The CTS function is the use of input on the CTSn# pin in transmission control. Setting the SECR.CTSE bit to 1 enables

the CTS function. When the CTS function is enabled, placing the low level on the CTSn# pin causes transmission to

Applying the low level to the CTS# pin while transmission is in progress does not affect transmission of the current

frame, which continues.

In the RTS function, by using the function of output on the RTSn# pin, a low level is output when reception becomes

possible. Conditions for output of the low and high level are shown below.

[Conditions for low-level output]

Satisfaction of all conditions listed below

• The value of the RE bit in the SCR is 1

• Reception is not in progress

• There are no received data yet to be read

• The ORER, FER, and PER flags in the SSR are all 0

[Condition for high-level output]

Any of the conditions for the low level not being satisfied

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

15. Serial Communications Interface

Rz/a1 series Rz/a1lu series Rz/a1lc series