Register Descriptions - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3

Register Descriptions

Table 10.3 shows the register configuration. To distinguish registers in each channel, an underscore and the channel
number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0.
Table 10.3 Register Configuration
Channel Register Name
0 Timer control register_0
Timer mode register_0
Timer I/O control register H_0
Timer I/O control register L_0
Timer interrupt enable register_0
Timer status register_0
Timer counter_0
Timer general register A_0
Timer general register B_0
Timer general register C_0
Timer general register D_0
Timer general register E_0
Timer general register F_0
Timer interrupt enable register 2_0
Timer status register 2_0
Timer buffer operation transfer mode register_0
1 Timer control register_1
Timer mode register_1
Timer I/O control register_1
Timer interrupt enable register_1
Timer status register_1
Timer counter_1
Timer general register A_1
Timer general register B_1
Timer input capture control register
2 Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable register_2
Timer status register_2
Timer counter_2
Timer general register A_2
Timer general register B_2
3 Timer control register_3
Timer mode register_3
Timer I/O control register H_3
Timer I/O control register L_3
Timer interrupt enable register_3
Timer status register_3
Timer counter_3
Timer general register A_3
Timer general register B_3
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
10. Multi-Function Timer Pulse Unit 2
Abbreviation R/W Initial value
TCR_0 R/W H'00
TMDR_0 R/W H'00
TIORH_0 R/W H'00
TIORL_0 R/W H'00
TIER_0 R/W H'00
TSR_0 R/W H'C0
TCNT_0 R/W H'0000
TGRA_0 R/W H'FFFF
TGRB_0 R/W H'FFFF
TGRC_0 R/W H'FFFF
TGRD_0 R/W H'FFFF
TGRE_0 R/W H'FFFF
TGRF_0 R/W H'FFFF
TIER2_0 R/W H'00
TSR2_0 R/W H'C0
TBTM_0 R/W H'00
TCR_1 R/W H'00
TMDR_1 R/W H'00
TIOR_1 R/W H'00
TIER_1 R/W H'00
TSR_1 R/W H'C0
TCNT_1 R/W H'0000
TGRA_1 R/W H'FFFF
TGRB_1 R/W H'FFFF
TICCR R/W H'00
TCR_2 R/W H'00
TMDR_2 R/W H'00
TIOR_2 R/W H'00
TIER_2 R/W H'00
TSR_2 R/W H'C0
TCNT_2 R/W H'0000
TGRA_2 R/W H'FFFF
TGRB_2 R/W H'FFFF
TCR_3 R/W H'00
TMDR_3 R/W H'00
TIORH_3 R/W H'00
TIORL_3 R/W H'00
TIER_3 R/W H'00
TSR_3 R/W H'C0
TCNT_3 R/W H'0000
TGRA_3 R/W H'FFFF
TGRB_3 R/W H'FFFF
Access
Address Size
H'FCFF0300 8
H'FCFF0301 8
H'FCFF0302 8
H'FCFF0303 8
H'FCFF0304 8
H'FCFF0305 8
H'FCFF0306 16
H'FCFF0308 16
H'FCFF030A 16
H'FCFF030C 16
H'FCFF030E 16
H'FCFF0320 16
H'FCFF0322 16
H'FCFF0324 8
H'FCFF0325 8
H'FCFF0326 8
H'FCFF0380 8
H'FCFF0381 8
H'FCFF0382 8
H'FCFF0384 8
H'FCFF0385 8
H'FCFF0386 16
H'FCFF0388 16
H'FCFF038A 16
H'FCFF0390 8
H'FCFF0000 8
H'FCFF0001 8
H'FCFF0002 8
H'FCFF0004 8
H'FCFF0005 8
H'FCFF0006 16
H'FCFF0008 16
H'FCFF000A 16
H'FCFF0200 8
H'FCFF0202 8
H'FCFF0204 8
H'FCFF0205 8
H'FCFF0208 8
H'FCFF022C 8
H'FCFF0210 16
H'FCFF0218 16
H'FCFF021A 16
10-6