Data Register (Spdr); Sequence Control Register (Spscr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.3.5

Data Register (SPDR)

SPDR is a buffer that holds data for transmission and reception.
The transmit buffer (SPTX) and receive buffer (SPRX) are independent and are mapped to SPDR.
SPDR should be read or written to in byte, word, or longword units according to the access width specification bit
(SPLW) in the data control register (SPDCR).
The bit length to be used is determined by the data length specification bits (SPB3 to SPB0) in the command register
(SPCMD).
The access width set by SPDCR must agree with the data length set by SPCMD.
When data is written to SPDR, the data will be written to the transmit buffer from SPDR if the transmit buffer has a space
equal to or more than the SPDR access width. If there is not enough space, data will not be written to the transmit buffer.
Even if an attempt is made to write data to the buffer, the data is ignored.
When data is read from SPDR, receive data in the receive buffer will be read. If SPDR is read when there is no receive
data in the receive buffer, the read value is undefined.
When SPDR is written to with the longword-, word-, or byte-access width, the transmit data should be written to address
0 irrespective of the access width. If data is written to the other addresses, the data is not guaranteed.
When SPDR is read with the longword-, word-, or byte-access width, the receive data should be read from address 0. If
data is read from the other addresses, the data is not guaranteed.
Bit: 31
SPD31 SPD30 SPD29 SPD28 SPD27 SPD26 SPD25 SPD24 SPD23 SPD22 SPD21 SPD20 SPD19 SPD18 SPD17 SPD16
Initial value:
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W: R/W
Bit:
15
SPD15 SPD14 SPD13 SPD12 SPD11 SPD10 SPD9
Initial value:
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
16.3.6

Sequence Control Register (SPSCR)

SPSCR sets the sequence control method when this module operates in master mode. If the contents of SPSCR are
changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in
master mode, the subsequent operation cannot be guaranteed.
Bit Bit Name
7 to 2 ―
1 SPSLN1
0 SPSLN0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
R/W R/W R/W R/W R/W
14 13 12 11 10
R/W R/W R/W R/W R/W
Bit: 7 6
⎯ ⎯
Initial value:
0 0
R/W: R R
Initial Value R/W
All 0 R
0 R/W
0 R/W
25 24 23 22 21
R/W R/W R/W R/W R/W
9 8 7 6 5
SPD8 SPD7 SPD6 SPD5 SPD4
R/W R/W R/W R/W R/W
5 4 3 2 1
SPS
⎯ ⎯ ⎯ ⎯
LN1
0 0 0 0 0
R R R R R/W
Function
Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
Sequence Length Specification
These bits specify a sequence length when this module in master mode
performs sequential operations. This module in master mode changes
command registers 0 to 3 (SPCMD0 to SPCMD3) to be referenced and
the order in which they are referenced according to the sequence length
that is set in the SPSLN1 and SPSLN0 bits.
The relationship among the setting of bits SPSLN1 and SPSLN0,
sequence length, and SPCMD0 to SPCMD3 referenced by this module is
shown below. In slave mode, SPCMD0 is always referenced.
Sequence
Length Referenced SPCMD #
00: 1 0 → 0 → ...
0 → 1 → 0 → ...
01: 2
0 → 1 → 2 → 0 → ...
10: 3
11: 4 0 → 1 → 2 → 3 → 0 → ...
16. Renesas Serial Peripheral Interface
20 19 18 17 16
R/W R/W R/W R/W R/W
4 3 2 1 0
SPD3 SPD2 SPD1 SPD0
R/W R/W R/W R/W R/W
0
SPS
LN0
0
R/W
16-10