18.13 Bus Hanging; Timeout Function - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

18.13 Bus Hanging

If the clock signals from the master and slave devices go out of synchronization due to noise or other
factors, the I
As measures against the bus hanging, the RIIC has a timeout function to detect hanging by monitoring
the SCL line, a function for the output of an extra SCL clock cycle to release the bus from a hung state
due to clock signals being out of synchronization, and the RIIC/internal reset function.
By checking the RIICnCR1.SCLO, SDAO, SCLI, and SDAI bits, it is possible to see whether the RIIC
or its partner in communications is placing the low level on the SCL or SDA lines.
18.13.1

Timeout Function

The RIIC has the timeout function to detect an abnormality that the SCL line is held for a certain period
of time. The RIIC can detect an abnormal bus state by monitoring that the SCL line is held low or high
for a predetermined time.
The timeout function monitors the SCL line state and counts the low-level period or high-level period
using the internal counter. The timeout function resets the internal counter each time the SCL line
changes (rising or falling), but continues to count unless the SCL line changes. If the internal counter
overflows due to no SCL line change, the RIIC can detect the timeout and report the bus abnormality.
This timeout function is enabled when the RIICnFER.TMOE bit is 1. It detects an abnormal bus state
in which the SCL line is held low or high in the following cases.
<1> The bus is busy (RIICnCR2.BBSY = 1) in master mode (RIICnCR2.MST = 1).
<2> The bus is busy (RIICnCR2.BBSY = 1) and the RIIC's own slave address matches (RIICnSR1 is
not 00
<3> The bus is free (RIICnCR2.BBSY = 0) and issuing of a start condition is being requested
(RIICnCR2.ST = 1).
The internal counter of the timeout function works using the internal reference clock (IICφ) set by the
RIICnMR1.CKS[2:0] bits as a count source. It functions as a 16-bit counter when long mode is
selected (RIICnMR2.TMOS bit = 0) or a 14-bit counter when short mode is selected (TMOS bit = 1).
The SCL line level (low/high or both levels) during which this counter is activated can be selected by
the setting of the RIICnMR2.TMOH and TMOL bits. If both TMOL and TMOH bits are cleared to 0,
the internal counter does not work.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
2
C bus might hang with a fixed level on the SCL line and/or SDA line.
) in slave mode (RIICnCR2.MST = 0).
H
18. I²C Bus Interface
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