Interrupt Ids - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Interrupt IDs

Table 7.3 lists the interrupt sources and their interrupt IDs, and the registers for setting the interrupt sources. Do not

make settings other than those in table 7.3, otherwise, the operation cannot be guaranteed.

Each interrupt source is allocated a different interrupt ID. To control notification of the interrupt source to the CPU and

reference its status, it is necessary to set and reference the following registers which correspond to given interrupt IDs.

• Interrupt security register

• Interrupt set-enable register

• Interrupt clear-enable register

• Interrupt set-pending register

• Interrupt clear-pending register

• Active bit register

• Interrupt configuration register

• Interrupt priority register

• Interrupt processor target register

For the procedure for the initial settings of the registers, see section 7.6.1 Initial Settings. For details on individual

registers, see the Arm Generic Interrupt Controller Architecture Specification and the PrimeCell

Controller (PL390) Technical Reference Manual from Arm.

List of Interrupt IDs

Interrupt Source

Request Source

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

7. Interrupt Controller

Generic Interrupt

Rz/a1 series Rz/a1lu series Rz/a1lc series