Download Print this page

Renesas RZ/A Series User Manual

Hide thumbs Also See for RZ/A Series:

User manual (78 pages)

,

Manuallines (19 pages)

,

User manual (49 pages)

Table Of Contents

page of 2866

/ 2866
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

Cover

RZ/A1L Group, RZ/A1LU Group,

32

RZ/A1LC Group

Renesas Microprocessor

RZ Family / RZ/A Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.6.00

Jan 2021

Table of Contents

Advertisement

Table of Contents

Need help?

Need help?

Do you have a question about the RZ/A Series and is the answer not in the manual?

Questions and answers

Summary of Contents for Renesas RZ/A Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
Page 3 Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 4: Table Of Contents
Contents Overview ............................1-1 Features of This LSI ..........................1-1 Product Lineup ............................1-9 Block Diagram.............................1-9 Pin Assignment..........................1-10 Pin Functions .............................1-14 List of Pins............................1-20 CPU ............................... 2-1 Features............................... 2-1 Configuration Signals ..........................2-2 Boot Mode............................3-1 Features..............................3-1 Boot Mode and Pin Function Setting ....................3-1 Hardware Used in Each Boot Mode ....................3-2 Exception Vector Address at a Reset in Each Boot Mode ..............3-3 Operation .............................3-4...
Page 5 Address Remapping...........................5-10 5.5.1 Overview ..........................5-10 5.5.2 Operation ..........................5-10 AXI Interconnect ..........................5-11 5.6.1 Configuration..........................5-11 5.6.2 Operation ..........................5-11 Bus Bridges............................5-11 AXI Protocol Control Signals......................5-12 5.8.1 Bus Masters other than Cortex-A9, CoreSight, and the Direct Memory Access Controller..5-12 5.8.2 Cortex-A9 ..........................5-12 5.8.3 CoreSight ..........................5-12 5.8.4 Direct Memory Access Controller....................5-13 5.8.5...
Page 6 6.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator ..........6-12 6.7.2 Oscillation Stabilizing Time of the PLL circuit ...............6-12 Notes on Board Design........................6-13 6.8.1 Note on Using a PLL Oscillation Circuit .................6-13 Definition of Modulation Rate and Frequency in the SSCG Specification........6-14 6.10 Clock Signals.............................6-15 6.10.1...
Page 7 Bus State Controller ........................8-1 Features..............................8-1 Input/Output Pins..........................8-3 Area Overview.............................8-4 8.3.1 Address Map..........................8-4 8.3.2 Data Bus Width and Related Pin Setting for Each Area Depending on Boot Mode....8-5 Register Descriptions...........................8-6 8.4.1 Common Control Register (CMNCR)..................8-7 8.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 5) ............8-8 8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 5)............8-10 8.4.4...
Page 8 9.4.8 Channel Control Register n (CHCTRL_n)................9-18 9.4.9 Channel Configuration Register n (CHCFG_n) ...............9-20 9.4.10 Channel Interval Register n (CHITVL_n)................9-22 9.4.11 Channel Extension Register n (CHEXT_n)................9-23 9.4.12 Next Link Address Register n (NXLA_n)................9-24 9.4.13 Current Link Address Register n (CRLA_n)................9-24 9.4.14 DMA Control Register (DCTRL_0_7, DCTRL_8_15) ............9-25 9.4.15 DMA Status EN Register (DSTAT_EN_0_7)................9-26...
Page 9 9.8.4 Setting Example 4 (Link Mode) ....................9-71 9.8.5 Next Register Set Continuous Execution Setting ..............9-74 Note ..............................9-76 9.9.1 Divided Output of DACK0 and TEND0 ..................9-76 9.9.2 TEND0 Not Output ........................9-77 9.9.3 Atomic Access (ARLOCK[1:0] and AWLOCK[1:0]).............9-77 Multi-Function Timer Pulse Unit 2 ....................10-1 10.1 Features..............................10-1 10.2...
Page 10 10.3.30 Bus Master Interface.......................10-60 10.4 Operation ............................10-61 10.4.1 Basic Functions........................10-61 10.4.2 Synchronous Operation ......................10-67 10.4.3 Buffer Operation........................10-69 10.4.4 Cascaded Operation........................10-73 10.4.5 PWM Modes...........................10-78 10.4.6 Phase Counting Mode......................10-82 10.4.7 Reset-Synchronized PWM Mode ...................10-88 10.4.8 Complementary PWM Mode....................10-91 10.4.9 A/D Converter Start Request Delaying Function ..............10-126 10.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ......10-129 10.5...
Page 11 10.7.21 Interrupts in Module Standby Mode..................10-151 10.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection......10-152 10.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode ...................10-152 10.8 Output Pin Initialization for Multi-Function Timer Pulse Unit 2..........10-154 10.8.1 Operating Modes ........................10-154 10.8.2...
Page 12 Realtime Clock..........................13-1 13.1 Features..............................13-1 13.2 Input/Output Pin ..........................13-3 13.3 Register Descriptions.........................13-3 13.3.1 64-Hz Counter (R64CNT) ......................13-4 13.3.2 Second Counter (RSECCNT)....................13-5 13.3.3 Minute Counter (RMINCNT)....................13-5 13.3.4 Hour Counter (RHRCNT) ......................13-6 13.3.5 Day of Week Counter (RWKCNT) ..................13-6 13.3.6 Day Counter (RDAYCNT).......................13-7 13.3.7 Month Counter (RMONCNT) ....................13-7 13.3.8...
Page 13 14.3.4 Transmit FIFO Data Register (SCFTDR) ................14-6 14.3.5 Serial Mode Register (SCSMR) ....................14-7 14.3.6 Serial Control Register (SCSCR) .....................14-9 14.3.7 Serial Status Register (SCFSR) ....................14-11 14.3.8 Bit Rate Register (SCBRR) ....................14-15 14.3.9 FIFO Control Register (SCFCR)....................14-19 14.3.10 FIFO Data Count Set Register (SCFDR) ................14-21 14.3.11 Serial Port Register (SCSPTR)....................14-22 14.3.12...
Page 14 15.3.3 Clock............................15-26 15.3.4 CTS and RTS Functions ......................15-26 15.3.5 SCI Initialization (Asynchronous Mode) ................15-27 15.3.6 Serial Data Transmission (Asynchronous Mode)..............15-28 15.3.7 Serial Data Reception (Asynchronous Mode) ................15-30 15.4 Multi-Processor Communications Function ..................15-34 15.4.1 Multi-Processor Serial Data Transmission ................15-35 15.4.2 Multi-Processor Serial Data Reception ..................15-36 15.5 Operation in Clock Synchronous Mode ..................15-39 15.5.1...
Page 15 Selection of High-Level Pulse Width..................15-68 15.13 Notes on Using the IrDA Module....................15-69 15.13.1 Shortest Pulse Width in Reception ..................15-69 15.13.2 Asynchronous Basic Clock for Serial Communication Interface...........15-69 Renesas Serial Peripheral Interface .................... 16-1 16.1 Features..............................16-1 16.2 Input/Output Pins..........................16-3 16.3 Register Descriptions.........................16-4 16.3.1...
Page 16 SPI Multi I/O Bus Controller ......................17-1 17.1 Features..............................17-1 17.2 Block Diagram...........................17-2 17.3 Input/Output Pins..........................17-3 17.4 Register Descriptions.........................17-4 17.4.1 Common Control Register (CMNCR)..................17-5 17.4.2 SSL Delay Register (SSLDR) ....................17-8 17.4.3 Bit Rate Register (SPBCR).......................17-9 17.4.4 Data Read Control Register (DRCR) ..................17-11 17.4.5 Data Read Command Setting Register (DRCMR) ..............17-12 17.4.6...
Page 17 17.5.12 SPBSSL Pin Control.......................17-52 17.5.13 Flags............................17-52 17.6 Usage Notes .............................17-53 17.6.1 Notes on Transfer to Read Data in SPI Operating Mode ............17-53 17.6.2 Notes on Starting Transfer from the SPBSSL Retained State in SPI Operating Mode..17-53 I²C Bus Interface .......................... 18-1 18.1 Features..............................18-1 18.1.1...
Page 18 18.9 Address Match Detection ........................18-67 18.9.1 Slave-Address Match Detection .....................18-67 18.9.2 Detection of the General Call Address ...................18-69 18.9.3 Device-ID Address Detection....................18-70 18.9.4 Host Address Detection ......................18-72 18.10 Automatically Low-Hold Function for SCL ...................18-73 18.10.1 Function to Prevent Wrong Transmission of Transmit Data..........18-73 18.10.2 NACK Reception Transfer Suspension Function..............18-74 18.10.3...
Page 19 19.4 Operation Description........................19-22 19.4.1 Bus Format ..........................19-22 19.4.2 Non-Compressed Modes ......................19-23 19.4.3 TDM Mode ..........................19-31 19.4.4 WS Continue Mode ........................19-32 19.4.5 Operation Modes ........................19-32 19.4.6 Transmit Operation.........................19-33 19.4.7 Receive Operation ........................19-36 19.4.8 Serial Bit Clock Control ......................19-38 19.5 Usage Notes .............................19-39 19.5.1 Limitations from Underflow or Overflow during DMA Operation ........19-39 19.5.2...
Page 20 21.3.15 RSCAN0GAFLP0j — Receive Rule Pointer 0 Register (j = 0 to 15)........21-48 21.3.16 RSCAN0GAFLP1j — Receive Rule Pointer 1 Register (j = 0 to 15)........21-50 21.3.17 RSCAN0RMNB — Receive Buffer Number Register ............21-51 21.3.18 RSCAN0RMNDy — Receive Buffer New Data Register y (y = 0) ........21-52 21.3.19 RSCAN0RMIDq —...
Page 21 21.3.46 RSCAN0TMTARSTSy — Transmit Buffer Transmit Abort Request Status Register y (y = 0) ........................21-92 21.3.47 RSCAN0TMTCSTSy — Transmit Buffer Transmit Complete Status Register y (y = 0) .............................21-93 21.3.48 RSCAN0TMTASTSy — Transmit Buffer Transmit Abort Status Register y (y = 0) ...21-94 21.3.49 RSCAN0TMIECy —...
Page 22 21.10.1 Initial Settings........................21-142 21.10.2 Reception Procedure......................21-148 21.10.3 Transmission Procedure .......................21-153 21.10.4 Test Settings .........................21-162 21.11 Notes on the RS-CAN Module ......................21-164 IEBus Controller........................... 22-1 22.1 IEBB Features............................22-1 22.2 Configuration.............................22-3 22.2.1 Function overview ........................22-3 22.2.2 Block diagram...........................22-4 22.3 Registers ............................22-5 22.3.1 IEBBn register overview ......................22-5 22.3.2 IEBBn control register details ....................22-6...
Page 23 Renesas SPDIF Interface ......................23-1 23.1 Overview ............................23-1 23.2 Features..............................23-1 23.3 Functional Block Diagram.........................23-2 23.4 Input/Output Pins..........................23-3 23.5 Renesas SPDIF (IEC60958) Frame Format ..................23-3 23.6 Register ..............................23-5 23.7 Register Descriptions.........................23-6 23.7.1 Control Register (CTRL)......................23-6 23.7.2 Status Register (STAT) ......................23-9 23.7.3 Transmitter Channel 1 Audio Register (TLCA)..............23-11...
Page 24 23.13.2 Frequency of Clock Input for Audio ..................23-28 CD-ROM Decoder........................24-1 24.1 Features..............................24-1 24.1.1 Formats Supported by CD-ROM Decoder ................24-2 24.2 Block Diagrams ..........................24-2 24.3 Register Descriptions.........................24-5 24.3.1 Enable Control Register (CROMEN)..................24-7 24.3.2 Sync Code-Based Synchronization Control Register (CROMSY0) ........24-8 24.3.3 Decoding Mode Control Register (CROMCTL0)..............24-9 24.3.4...
Page 25 24.3.36 Post-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD23) .....24-25 24.3.37 Post-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD24)..24-25 24.3.38 Post-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD25)...24-25 24.3.39 Post-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD26) .....24-26 24.3.40 Post-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD27) .....24-26 24.3.41...
Page 26 25.1.3 Clock Supply ..........................25-1 25.1.4 Interrupts and DMA........................25-2 25.1.5 I/O Signals ..........................25-2 25.2 Function .............................25-3 25.2.1 Block Diagram..........................25-5 25.2.2 Description of Blocks .......................25-5 25.3 Registers ............................25-6 25.3.1 LIN Master Related Registers ....................25-7 25.4 Interrupt Sources..........................25-33 25.5 Modes ..............................25-34 25.6 LIN Reset Mode ..........................25-36 25.7 LIN Mode ............................25-37 25.7.1...
Page 27 26.3.12 Too-Long Frame Receive Counter Register (TLFRCR)............26-16 26.3.13 Residual-Bit Frame Receive Counter Register (RFCR)............26-17 26.3.14 Multicast Address Frame Receive Counter Register (MAFCR) ..........26-17 26.3.15 Automatic PAUSE Frame Register (APR)................26-18 26.3.16 Manual PAUSE Frame Register (MPR).................26-19 26.3.17 Automatic PAUSE Frame Retransmit Count Register (TPAUSER) ........26-19 26.3.18 PAUSE Frame Transmit Counter Register (PFTCR).............26-20 26.3.19...
Page 28 26.3.53 Transmit Descriptor Final Flag Register (TDFFR) ..............26-52 26.3.54 Overflow Alert FIFO Threshold Register (FCFTR)...............26-53 26.3.55 Receive Data Padding Insert Register (RPADIR)..............26-54 26.3.56 Intelligent Checksum Mode Register (CSMR) ..............26-55 26.3.57 Intelligent Checksum Skipped Bytes Monitor Register (CSSBM) ........26-56 26.3.58 Intelligent Checksum Monitor Register (CSSMR) ..............26-56 26.4 Operation ............................26-57 26.4.1...
Page 29 27.4.6 External Trigger Input Timing ....................27-20 27.5 Interrupt Sources and DMA Transfer Request ................27-21 27.6 Definitions of A/D Conversion Accuracy ..................27-22 27.7 Usage Notes .............................27-23 27.7.1 Module Standby Mode Setting ....................27-23 27.7.2 Setting Analog Input Voltage ....................27-23 27.7.3 Notes on Board Design......................27-23 27.7.4 Processing of Analog Input Pins ....................27-24 27.7.5...
Page 30 28.3.27 USB Request Length Register (USBLENG)................28-44 28.3.28 DCP Configuration Register (DCPCFG) ................28-44 28.3.29 DCP Maximum Packet Size Register (DCPMAXP)..............28-47 28.3.30 DCP Control Register (DCPCTR)..................28-48 28.3.31 Pipe Window Select Register (PIPESEL) ................28-52 28.3.32 Pipe Configuration Register (PIPECFG)................28-53 28.3.33 Pipe Buffer Setting Register (PIPEBUF) ................28-57 28.3.34 Pipe Maximum Packet Size Register (PIPEMAXP) ..............28-59 28.3.35...
Page 31 30.1.4 Controlling Externally Input Video Signals ................30-3 30.1.5 Selecting Clock Edge for Externally Input Signals ..............30-4 30.1.6 Externally Input Sync Signal Inversion Control...............30-4 30.1.7 Bit Allocation of Externally Input Video Image Signals ............30-5 30.1.8 Typical Signal Timing of BT601 Format .................30-9 30.1.9 Typical Signal Timing of BT656 Format ................30-12 30.1.10...
Page 32 31.1.1 Overview of Functions ......................31-1 31.1.2 Register Control........................31-2 31.1.3 Synchronization Control......................31-3 31.1.4 Setting Angle of View ......................31-8 31.1.5 Scaling Settings ........................31-12 31.1.6 Horizontal Prefilter .........................31-14 31.1.7 Horizontal Scale-Down ......................31-14 31.1.8 Vertical Scale-Down.......................31-16 31.1.9 Horizontal Scale Up........................31-18 31.1.10 Vertical Scale-Up ........................31-19 31.1.11 IP Conversion .........................31-21 31.1.12...
Page 33 31.2.20 Output Image Vertical Size Register (SC0_SCL0_US2) ............31-54 31.2.21 Output Image Horizontal Size Register (SC0_SCL0_US3)...........31-55 31.2.22 Scaling-Up Control Block Input Size Register (SC0_SCL0_US4)........31-56 31.2.23 Horizontal Scale Up Register (SC0_SCL0_US5) ..............31-56 31.2.24 Horizontal Scale Up Initial Phase Register (SC0_SCL0_US6) ..........31-57 31.2.25 Trimming Register (SC0_SCL0_US7)...................31-57 31.2.26 Frame Buffer Read Select Register (SC0_SCL0_US8) ............31-58...
Page 34 31.2.61 Alpha Blending Control Register 10 (Graphics 0) (GR0_AB10) ..........31-85 31.2.62 Alpha Blending Control Register 11 (Graphics 0) (GR0_AB11) ..........31-86 31.2.63 Background Color Control Register (Graphics 0) (GR0_BASE) ..........31-86 31.2.64 CLUT Table Control Register (Graphics 0) (GR0_CLUT) ...........31-87 31.3 Usage Method..........................31-88 31.3.1 Scaling Setting Example for 525i Video Input and VGA-Size (640 x 480) Video Output ...31-88 31.3.2...
Page 35 Video Display Controller 5 (5): Image Synthesizer ..............33-1 33.1 Image Synthesizer..........................33-1 33.1.1 Overview of Functions ......................33-1 33.1.2 Graphics Data Read Control.....................33-2 33.1.3 Setting Graphics Display Area ....................33-12 33.1.4 Interrupt Generation at Specified Line ...................33-13 33.1.5 Formats of Frame Buffer Read Signals and Corresponding Alpha Blending Types .....33-13 33.1.6 Display Selection........................33-14 33.1.7...
Page 36 33.2.22 Status Monitor Register (Graphics 2) (GR2_MON) ..............33-40 33.2.23 Graphics 3 Register Update Control Register (GR3_UPDATE) ...........33-41 33.2.24 Frame Buffer Read Control Register (Graphics 3) (GR3_FLM_RD)........33-41 33.2.25 Frame Buffer Control Register 1 (Graphics 3) (GR3_FLM1) ..........33-42 33.2.26 Frame Buffer Control Register 2 (Graphics 3) (GR3_FLM2) ..........33-43 33.2.27 Frame Buffer Control Register 3 (Graphics 3) (GR3_FLM3) ..........33-43 33.2.28...
Page 37 34.2.2 Function Switch Register in Gamma Correction Block (GAM_SW) ........34-31 34.2.3 Table Setting Register G1 to G16 in Gamma Correction Block (GAM_G_LUT1 to GAM_G_LUT16) ..................34-32 34.2.4 Area Setting Register G1 in Gamma Correction Block (GAM_G_AREA1)......34-34 34.2.5 Area Setting Register G2 in Gamma Correction Block (GAM_G_AREA2)......34-35 34.2.6 Area Setting Register G3 in Gamma Correction Block (GAM_G_AREA3)......34-36 34.2.7...
Page 38 34.2.41 TCON Horizontal Timing Setting Register STB2 (TCON_TIM_STB2) ......34-72 34.2.42 TCON Horizontal Timing Setting Register CPV1 (TCON_TIM_CPV1) ......34-73 34.2.43 TCON Horizontal Timing Setting Register CPV2 (TCON_TIM_CPV2) ......34-74 34.2.44 TCON Horizontal Timing Setting Register POLA1 (TCON_TIM_POLA1) ......34-75 34.2.45 TCON Horizontal Timing Setting Register POLA2 (TCON_TIM_POLA2) ......34-76 34.2.46 TCON Horizontal Timing Setting Register POLB1 (TCON_TIM_POLB1) ......34-77 34.2.47...
Page 39 36.4.5 Capture Interface Offset Register (CAMOR).................36-17 36.4.6 Capture Interface Width Register (CAPWR) .................36-19 36.4.7 Capture Interface Input Format Register (CAIFR)..............36-21 36.4.8 CEU Register Control Register (CRCNTR)................36-25 36.4.9 CEU Register Forcible Control Register (CRCMPR)............36-26 36.4.10 Capture Filter Control Register (CFLCR) ................36-27 36.4.11 Capture Filter Size Clip Register (CFSZR)................36-29 36.4.12...
Page 40 37.3.9 FFD0_n FIFO Download Boot Register (FFDBR_FFD0_n) (n = 0, 1, 2, 3)......37-15 37.3.10 FFD0_n FIFO Download Event Mask Register (DEVMR_FFD0_n) (n = 0, 1, 2, 3)....37-16 37.3.11 FFD0_n FIFO Download Event Clear Register (DEVCR_FFD0_n) (n = 0, 1, 2, 3).....37-17 37.3.12 FFU0_n FIFO Upload Initialization Register (FFUIR_FFU0_n) (n = 0, 1, 2, 3) ....37-18 37.3.13...
Page 41 37.3.50 DVU0_n Event Mask Register (VEVMR_DVU0_n) (n = 0, 1, 2, 3) ........37-52 37.3.51 DVU0_n Event Clear Register (VEVCR_DVU0_n) (n = 0, 1, 2, 3) ........37-54 37.3.52 MIX0_0 Initialization Register (MIXIR_MIX0_0) ...............37-55 37.3.53 MIX0_0 Audio Information Register (MADIR_MIX0_0) ............37-56 37.3.54 MIX0_0 Bypass Register (MIXBR_MIX0_0) ...............37-57 37.3.55 MIX0_0 Mode Register (MIXMR_MIX0_0) ................37-57...
Page 42 38.2 Register Descriptions.........................38-3 38.2.1 Command Type Register (SD_CMD) ..................38-5 38.2.2 SD Command Argument Registers (SD_ARG) ...............38-6 38.2.3 Data STOP Register (SD_STOP) .....................38-7 38.2.4 Block Count Register (SD_SECCNT) ..................38-8 38.2.5 SD Card Response Registers (SD_RSP) ..................38-8 38.2.6 SD Card Interrupt Flag Register 1 (SD_INFO1)..............38-10 38.2.7 SD Card Interrupt Flag Register 2 (SD_INFO2)..............38-12 38.2.8...
Page 43 MMC Host Interface ........................39-1 39.1 Features..............................39-1 39.2 Input/Output Pins..........................39-1 39.3 Register Descriptions.........................39-2 39.3.1 Command Setting Register (CE_CMD_SET)................39-3 39.3.2 Argument Register (CE_ARG) ....................39-5 39.3.3 Argument Register for Automatically-Issued CMD12 (CE_ARG_CMD12) ......39-5 39.3.4 Command Control Register (CE_CMD_CTRL)..............39-6 39.3.5 Transfer Block Setting Register (CE_BLOCK_SET) ..............39-6 39.3.6 Clock Control Register (CE_CLK_CTRL) ................39-7 39.3.7...
Page 44 39.7.7 Multi-Block Read (with Automatic CMD12 Issuance)............39-35 39.7.8 Single-Block Write .........................39-36 39.7.9 Multi-Block Write .........................39-37 39.7.10 Multi-Block Write (with Automatic CMD12 Issuance)............39-38 39.7.11 Forcible Termination ......................39-39 39.7.12 Setting Values of CE_CMD_SET ..................39-40 39.8 Usage Note ............................39-42 39.8.1 Card Detection........................39-42 39.8.2 Multi-Block Transfer......................39-42 39.8.3 Software Reset........................39-42...
Page 45 41.6 Port 0 (P0)............................41-15 41.7 Port 1 (P1)............................41-16 41.8 Port 2 (P2)............................41-17 41.9 Port 3 (P3)............................41-18 41.10 Port 4 (P4)............................41-19 41.11 Port 5 (P5)............................41-20 41.12 Port 6 (P6)............................41-21 41.13 Port 7 (P7)............................41-23 41.14 Port 8 (P8)............................41-24 41.15 Port 9 (P9)............................41-25 41.16 Port Control Logical Diagram ......................41-26 41.17...
Page 46 42.2.26 Deep Standby Cancel Edge Select Register (DSESR) ............42-30 42.2.27 Deep Standby Cancel Source Flag Register (DSFR) .............42-31 42.2.28 XTAL Crystal Oscillator Gain Control Register (XTALCTR)..........42-32 42.3 Operation ............................42-33 42.3.1 Sleep Mode ..........................42-33 42.3.2 Software Standby Mode ......................42-34 42.3.3 Software Standby Mode Application Example ..............42-36 42.3.4 Deep Standby Mode .......................42-36 42.3.5...
Page 47 44.2.2 JPEG Code Command Register (JCCMD)................44-5 44.2.3 JPEG Code Quantization Table Number Register (JCQTN) ...........44-6 44.2.4 JPEG Code Huffman Table Number Register (JCHTN)............44-7 44.2.5 JPEG Code DRI Upper Register (JCDRIU)................44-7 44.2.6 JPEG Code DRI Lower Register (JCDRID) ................44-8 44.2.7 JPEG Code Vertical Size Upper Register (JCVSZU) ..............44-8 44.2.8 JPEG Code Vertical Size Lower Register (JCVSZD)..............44-8 44.2.9...
Page 48 44.5 Bus Reset Processing........................44-46 EthernetAVB ..........................45-1 45.1 Overview ............................45-1 45.1.1 Specifications (Functions) ......................45-1 45.1.2 Block Diagram..........................45-2 45.1.3 I/O Pins .............................45-3 45.2 Register Descriptions.........................45-4 45.2.1 AVB-DMAC Mode Register (CCC) ..................45-6 45.2.2 Descriptor Base Address Table Register (DBAT) ..............45-9 45.2.3 Descriptor Base Address Load Request Register (DLR) ............45-10 45.2.4 AVB-DMAC Status Register (CSR) ..................45-13 45.2.5...
Page 49 45.2.35 Receive Interrupt Status Register 2 (RIS2) ................45-63 45.2.36 Transmit Interrupt Control Register (TIC) ................45-66 45.2.37 Transmit Interrupt Status Register (TIS) ................45-67 45.2.38 Interrupt Summary Status Register (ISS) ................45-69 45.2.39 gPTP Configuration Control Register (GCCR)..............45-72 45.2.40 gPTP Maximum Transit Time Configuration Register (GMTT) ...........45-75 45.2.41 gPTP Presentation Time Comparison Register (GPTC) ............45-76 45.2.42...
Page 50 Watchdog Timer Timing ......................47-41 47.4.7 Serial Communication Interface with FIFO Timing ..............47-42 47.4.8 Serial Communication Interface Timing ................47-43 47.4.9 Renesas Serial Peripheral Interface Timing ................47-44 47.4.10 SPI Multi I/O Bus Controller Timing..................47-47 47.4.11 I²C Bus Interface Timing......................47-50 47.4.12 Serial Sound Interface Timing....................47-51 47.4.13...
Page 51 48.2 Treatment of Unused Pins .........................48-6 48.3 Handling of Pins in Deep Standby Mode ..................48-7 48.4 Recommended Combination of Bypass Capacitor ................48-8 Appendix ............................ Appendix-1 Package Dimensions ......................Appendix-1 Revision History ......................Revision History-1...
Page 52: Overview
C bus interface, serial sound interface, media local bus (RZ/A1L only), SCUX, CAN interface, IEBus™* controller (RZ/A1L only), Renesas SPDIF interface, Renesas serial peripheral interface, SPI multi I/O bus controller, CD-ROM decoder (RZ/A1L only), A/D converter, LIN interface (RZ/A1L only), Ethernet controller, EthernetAVB (RZ/A1LU only), USB 2.0 host/function, video display controller 5, JPEG codec unit (RZ/A1LU only),...
Page 53 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Table 1.1 Features of RZ/A1L, RZ/A1LU, and RZ/A1LC Items Specification • Arm Cortex-A9 processor • Maximum operating frequency: 400 MHz • Instruction cache size: 32 Kbytes • Data cache size: 32 Kbytes (write-back algorithm) •...
Page 54 • Modem control function • Encoding and decoding of IrDA communications waveforms in accord with version 1.0 of the IrDA standard (on channel 0) • Three channels Renesas serial peripheral • SPI operation interface • Master mode and slave mode selectable •...
Page 55 Note: Input of peripheral clock 0 (P0φ) running at 32 MHz is required. • Support of IEC60958 standard (stereo and consumer use modes only) Renesas SPDIF interface • Sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz • Audio word sizes of 16 to 24 bits per sample •...
Page 56 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Items Specification CD-ROM decoder • Support of five formats: Mode 0, mode 1, mode 2, mode 2 form 1, and mode 2 form 2 (RZ/A1L only) • Sync codes detection and protection (Protection: When a sync code is not detected, it is automatically inserted.) •...
Page 57 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Items Specification Video display controller 5 • Scaling control Vertical and horizontal scaling up or down of input video possible at a desired ratio (scaling up of graphics also possible) Scaling up ratio: 1 to 8; scaling down ratio: 1/8 to 1 Interpolation: Hold or linear selectable 2D IP conversion: 2D IP conversion through separately setting the initial phases for the top and bottom fields...
Page 58 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Items Specification Capture engine unit • Examples of input video image size : 5 megapixels (2,560 × 1,920), 3 megapixels (2,048 × 1,536), 2 megapixels (1,632 × 1,224), UXGA (1,600 × 1,200), SXGA (1) (1,280 ×...
Page 59 JEITA package code: P-LFQFP176-24×24-0.50 RENESAS code: PLQP0176KB-A • PLQP0208KB-A 208-pin QFP, 28-mm square, 0.5-mm pitch JEITA package code: P-LFQFP208-28×28-0.50 RENESAS Code : PLQP0208KB-A • PRBG0233GA-A 233-pin BGA, 15-mm square, 0.8-mm pitch JEITA package code: P-FBGA233-15x15-0.80 RENESAS Code : PRBG0233GA-A R01UH0437EJ0600 Rev.6.00...
Page 60: Product Lineup
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Product Lineup Table 1.2 Product Lineup Group Part Number Temperature Range Quality Level Package RZ/A1L R7S721020VCBG -40 to +85°C Industry usage etc. PLBG0176KA-A R7S721020VCFP Industry usage etc. PLQP0176KB-A R7S721020VLFP Car Accessories R7S721021VCFP Industry usage etc.
Page 61: Pin Assignment
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Pin Assignment P5_2 P5_0 P4_5 P4_3 USB_X1 P2_8 P3_15 P5_3 P5_1 P4_6 P4_4 P4_1 REFRIN USB_X2 P2_9 P2_6 P1_7 P5_6 P5_4 P4_7 P4_2 P4_0 USBAVcc VBUS0 VBUS1 P2_7 P1_6 P1_5 P5_7 P5_5 P5_8 PVcc USBAPVcc...
Page 62 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 P3_15 AVref P2_6...
Page 63 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 P3_15 AVref P2_6...
Page 64 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview P5_2 P5_0 P4_6 P4_5 P4_2 P4_0 USB_X1 P2_6 P3_15 P5_3 P5_1 P8_5 P8_2 P8_1 P4_3 REFRIN USB_X2 P2_8 P2_7 PVcc P5_7 P5_4 P4_7 P8_4 P4_4 P8_0 P4_1 USBAVcc VBUS0 VBUS1 PVcc P2_9 PVcc P1_7 P5_10...
Page 65: Pin Functions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Pin Functions Table 1.3 Pin Functions Classification Symbol Name Function Power supply Power supply Power supply pins. All the Vcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open.
Page 66 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Classification Symbol Name Function System control Power-on reset This LSI enters the power-on reset state when this signal goes low. WDTOVF Watchdog timer Outputs an overflow signal from the overflow watchdog timer. Interrupts Non-maskable Non-maskable interrupt request pin.
Page 67 Data input pins. SCI_RXD0 SCI_CTS1/RTS1, Transmit and receive I/O pins for controlling the start of SCI_CTS0/RTS0 start control transmission and reception. Renesas serial MOSI2 to MOSI0 Data Data I/O pins. peripheral interface MISO2 to MISO0 Data Data I/O pins. RSPCK2 to RSPCK0 Clock Clock I/O pins.
Page 68 Output pin for transmit data on IEBus™ (RZ/A1L only) transmit data controller. IERxD IEBus™ controller Input pin for receive data on IEBus™ receive data controller. Renesas SPDIF SPDIF_OUT Output data Transmit data output pin. interface SPDIF_IN Input data Receive data input pin. LIN interface...
Page 69 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Classification Symbol Name Function USB 2.0 host/ DP1, DP0 USB 2.0 host/function D+ data pins for USB 2.0 host/function function module module D+ data module bus. DM1, DM0 USB 2.0 host/function D– data pins for USB 2.0 host/function module D–...
Page 70 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Classification Symbol Name Function Capture engine unit VIO_D7 to VIO_D0 Input data Graphics data input pins. VIO_CLK Input clock Graphics data clock input pin. VIO_VD VSYNC input VSYNC input pin. VIO_HD HSYNC input HSYNC input pin.
Page 71: List Of Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview List of Pins Table 1.4 List of Pins Simplified Port function/ Mode function Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Circuit dedicated function Diagram Symbol Symbol...
Page 72 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Simplified Port function/ Mode function Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Circuit dedicated function Diagram Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol...
Page 73 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Simplified Port function/ Mode function Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Circuit dedicated function Diagram Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol...
Page 74 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Simplified Port function/ Mode function Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Circuit dedicated function Diagram Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol...
Page 75 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Simplified Port function/ Mode function Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Circuit dedicated function Diagram Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol...
Page 76 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Schmitt input data Figure 1.5 (1) Simplified Circuit Diagram (Schmitt Input Buffer) TTL input data TTL input enable Figure 1.5 (2) Simplified Circuit Diagram (TTL AND Input Buffer) Schmitt input data Schmitt input enable Figure 1.5 (3) Simplified Circuit Diagram (Schmitt AND Input Buffer) A/D analog input enable...
Page 77 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Latch enable Output enable Output data TTL input data TTL input enable Figure 1.5 (6) Simplified Circuit Diagram (Bidirectional Buffer, TTL AND Input, with Latch) Latch enable Output enable Output data Schmitt input data Schmitt input enable Figure 1.5 (7) Simplified Circuit Diagram (Bidirectional Buffer, Schmitt AND Input, with Latch)
Page 78 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 1. Overview Output data Schmitt input data Schmitt input enable Figure 1.5 (9) Simplified Circuit Diagram (Open Drain Output and Schmitt OR Input Buffer) Input clock XOUT (XTAL, AUDIO_X2, USB_X2) (EXTAL, AUDIO_X1, USB_X1) Input enable Figure 1.5 (10) Simplified Circuit Diagram (Oscillation Buffer 1) XOUT...
Page 79: Cpu
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 2. CPU This product incorporates the Arm single-core Cortex-A9 MPCore, where the IP version is r3p0. Features • Instruction cache size: 32 Kbytes • Data cache size : 32 Kbytes • TLB entries: 128 entries •...
Page 80: Configuration Signals
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 2. CPU Configuration Signals Table 2.1 shows the Cortex-A9 configuration signals and the settings. Table 2.1 Cortex-A9 Configuration Signal Settings Configuration Signal Setting Values CFGEND 1’b0 CFGNMIF 1’b1 CLUSTERID 4'h0 FILTEREN* 1’b1 FILTERSTART[31:20]* 12’hE00 FILTEREND[31:20]* 12’hFFF PERIPHBASE[31:13]*...
Page 81: Boot Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 3. Boot Mode Boot Mode This LSI can be booted from the memory connected to the CS0 space and the serial flash memory. Note 1. Booting from the NAND flash memory with an SD controller and the NAND flash memory with an MMC controller are not currently supported.
Page 82: Hardware Used In Each Boot Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 3. Boot Mode Hardware Used in Each Boot Mode Table 3.2 gives information about the hardware used in each boot mode. Table 3.2 Hardware Used in Each Boot Mode Boot Mode Peripheral Module Pins Used Remarks Boot Mode 0 Bus state controller...
Page 83: Exception Vector Address At A Reset In Each Boot Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 3. Boot Mode Exception Vector Address at a Reset in Each Boot Mode In this LSI, the exception vector address at a reset differs depending on the boot mode. In this LSI, the exception vector at a reset starts from H'0000_0000 (low vector) in boot mode 0 and from H'FFFF_0000 (high vector) in boot modes 1 to 3.
Page 84: Boot Mode 1
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 3. Boot Mode Operation 3.5.1 Boot Mode 0 In boot mode 0, this LSI is booted from the memory connected to the CS0 space. In these modes, this LSI operates as follows: After the power-on reset is canceled, program execution is started from H'0000_0000 in the memory connected to the CS0 space.
Page 85: Boot Mode 2
NAND flash memory with the SD controller according to the loader program storage specifications.* Note 1. For the storage specifications of the loader program, contact Renesas Electronics Corporation's sales office. After the boot program finishes processing, it branches to H'2002_4000 (large-capacity on-chip RAM). At this time, the...
Page 86 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 3. Boot Mode Figure 3.2 is a schematic view of the specification for boot mode 2. This LSI NAND flash memory with SD controller (1) Run the boot program H'FFFF_0000 Loader program SD host interface Read On-chip ROM (28 KB)
Page 87: Boot Mode 3
NAND flash memory with the MMC controller according to the loader program storage specifications.* Note 1. For the storage specifications of the loader program, contact Renesas Electronics Corporation's sales office. After the boot program finishes processing, it branches to H'2002_4000 (large-capacity on-chip RAM). At this time, the...
Page 88 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 3. Boot Mode Figure 3.3 is a schematic view of the specification for boot mode 3. This LSI NAND flash memory with MMC controller (1) Run the boot program H'FFFF_0000 Read Loader program MMC host interface On-chip ROM (28 KB) (2) Loading into...
Page 89: Notes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 3. Boot Mode Notes 3.6.1 Boot Related Pins The initial states and output states in deep standby mode of the pins related to CS0 space memory read, SPI multi I/O bus space memory read, channel 0 of the SD host interface, and the MMC host interface are different in each boot mode. For details, refer to section 8, Bus State Controller, section 41, Ports, and section 42, Power-Down Modes.
Page 90: Secondary Cache
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 4. Secondary Cache Secondary Cache This product incorporates Arm's PL310 as a secondary cache. The IP version is r3p2. Features • Total cache size: 128 Kbytes • Number of cache ways: 8 ways • Number of master ports : •...
Page 91: Lsi Internal Bus
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus LSI Internal Bus LSI Internal Bus 5.1.1 Configuration This LSI has two main buses: the north main bus where peripheral modules are connected and the south main bus where on-chip RAM and external ROM and RAM are connected. Figure 5.1 is a schematic diagram of the internal buses. This LSI Cortex-A9 Bus masters...
Page 92: North Main Bus
SLV5 SLV6 SLV7 SLV8 OpenVG Write Write Write Write Write AXI64IC2 bus compliant buffer buffer buffer buffer buffer Renesas graphics Write Direct Interrupt processor On-chip memory access controller buffer controller bridge 1 bridge 2 AHB32IC3 bus Peripheral Peripheral Peripheral Peripheral...
Page 93: Peripheral Buses
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.2.3 Peripheral Buses Table 5.2 is a list of the peripheral buses connected to the north main bus. Table 5.2 List of Peripheral Buses Item Description Peripheral bus 1 Bus clock frequency P0φ...
Page 94 32 bits Connected peripheral modules Serial communication interface with FIFO channels 0 to 4 Serial communication interface channels 0 and 1 Renesas serial peripheral interface channels 0 to 2 Renesas SPDIF interface CD-ROM decoder (RZ/A1L only) A/D converter USB2.0 host/function module channel 0...
Page 95: South Main Bus
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus South Main Bus 5.3.1 Configuration On-chip RAM and external ROM and RAM are connected to the south main bus. Figure 5.3 shows the configuration of the south main bus. North main bus Video display Video display controller 5...
Page 96: Connected Buses
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.3.3 Connected Buses Table 5.4 is a list of the buses connected to the south main bus and their features. Table 5.4 List of Buses Connected to South Main Bus and their Features Item Description AXI128IC2 and AXI128IC3 buses...
Page 97: Address Map
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus Address Map Table 5.5 shows the address map of this LSI. Table 5.5 Address Map Slave Area Viewed Slave Area Viewed from North Main Bus from South Main Bus Address Area Masters Masters...
Page 98 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus Table 5.5 Address Map Slave Area Viewed Slave Area Viewed from North Main Bus from South Main Bus Address Area Masters Masters 0x5800_0000 to SPI multi I/O bus area SLV7 SLV1 0x5BFF_FFFF mirror area (64 Mbytes)
Page 99 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus Note 1. Only Cortex-A9, the direct memory access controller, and CoreSight can access this area. If any other north main bus master accesses this area, a decode error will occur. Note 2.
Page 100: Address Remapping
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus Address Remapping 5.5.1 Overview Execution in Cortex-A9 jumps to an exception vector placed in addresses 0x0000_0000 to 0x0000_001C when an exception such as a reset or an interrupt occurs. The interrupt response time depends on the time to access the memory connected to this area, and when low-speed memory is connected, the overhead is large.
Page 101: Axi Interconnect
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus AXI Interconnect 5.6.1 Configuration The AXI interconnect in this LSI has a multi-layer configuration in all channels (five channels). Figure 5.5 shows a conceptual diagram of the AXI interconnect configuration. Bus master 0 Bus master 1 AXI interconnect...
Page 102: Axi Protocol Control Signals
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus AXI Protocol Control Signals The AXI protocol control signals can be set as desired for each bus master. For details of the AXI protocol control signals, refer to the AMBA AXI Protocol Specification prepared by Arm Ltd. 5.8.1 Bus Masters other than Cortex-A9, CoreSight, and the Direct Memory Access Controller...
Page 103: Direct Memory Access Controller
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus (2) Response unit (RRESP[1:0], BRESP[1:0]) OKAY is returned when RRESP[1:0] and BRESP[1:0] are 00 or 01. ERROR is returned when RRESP[1:0] and BRESP[1:0] are 10 or 11. (3) Protection unit information (ARPROT[2:0], AWPROT[2:0]) ARPROT[2], AWPROT[2]: Inverse of HPROT[0] (data/opcode) ARPROT[1], AWPROT[1]: Fixed to 1 (non-secure access) ARPROT[0], AWPROT[0]: Value of HPROT[1] (privileged)
Page 104: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10 Register Descriptions Table 5.6 shows the registers related to the internal bus. Table 5.6 Register Configuration Access Register Name Abbreviation Initial Value Address Size Remap register RMPR H'0000_0003 H’FCFE_1A00 AXI bus control register 0 AXIBUSCTL0 H'0000_0000...
Page 105: Remap Register (Rmpr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.1 Remap Register (RMPR) This register controls the address remapping function. Bit: — — — — — — — — — — — — — — — — Initial value: R/W: Bit: —...
Page 106: Axi Bus Control Register 0 (Axibusctl0)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.2 AXI Bus Control Register 0 (AXIBUSCTL0) This register controls the cache operation for the JPEG codec unit (RZ/A1LU only) and Ethernet controller. Bit: — — — — JCUARCACHE[3:0]* — —...
Page 107: Axi Bus Control Register 2 (Axibusctl2)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.3 AXI Bus Control Register 2 (AXIBUSCTL2) This register controls the cache operation for the capture engine unit. Bit: — — — — — — — — — — — —...
Page 108: Axi Bus Control Register 6 (Axibusctl6)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.5 AXI Bus Control Register 6 (AXIBUSCTL6) This register controls the cache operation for video display controller 5. Bit: — — — — VDC501ARCACHE[3:0] — — — — VDC501AWCACHE[3:0] Initial value: R/W: Bit: —...
Page 109: Axi Bus Control Register 7 (Axibusctl7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.6 AXI Bus Control Register 7 (AXIBUSCTL7) This register controls the cache operation for video display controller 5. Bit: — — — — — — — — — — — —...
Page 110: Axi Bus Response Error Interrupt Control Register 0 (Axirerrctl0)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.7 AXI Bus Response Error Interrupt Control Register 0 (AXIRERRCTL0) This register controls AXI bus response error interrupts. Bit: JCUR ETHR — — — — — — — — — —...
Page 111: Axi Bus Response Error Interrupt Control Register 2 (Axirerrctl2)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.8 AXI Bus Response Error Interrupt Control Register 2 (AXIRERRCTL2) This register controls AXI bus response error interrupts. Bit: VDC501 VDC502 VDC504 — — — — — — — — —...
Page 112: Axi Bus Response Error Status Register 0 (Axirerrst0)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.9 AXI Bus Response Error Status Register 0 (AXIRERRST0) This register indicates occurrence of AXI bus response errors. Bit: JCURRESP JCUBRESP ETHRRESP ETHBRESP — — — — — — — —...
Page 113: Axi Bus Response Error Status Register 2 (Axirerrst2)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.10 AXI Bus Response Error Status Register 2 (AXIRERRST2) This register indicates occurrence of AXI bus response errors. Bit: VDC501RRESP VDC501BRESP VDC502RRESP VDC504RRESP — — — — — — — —...
Page 114: Axi Bus Response Error Clear Register 0 (Axirerrclr0)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.11 AXI Bus Response Error Clear Register 0 (AXIRERRCLR0) This register clears the AXI bus response error status. Bit: — RRESP — BRESP — — — — — — — —...
Page 115: Axi Bus Response Error Clear Register 2 (Axirerrclr2)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.10.12 AXI Bus Response Error Clear Register 2 (AXIRERRCLR2) This register clears the AXI bus response error status. Bit: VDC501 VDC501 VDC502 VDC504 — — — — — — — —...
Page 116: Interrupt Request
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 5. LSI Internal Bus 5.11 Interrupt Request When a decode error or a slave error occurs, an AXI bus response error interrupt request (PRRI) is issued. An interrupt request is issued when a response is returned from the bus for which interrupt requests are enabled through the AXI bus response error interrupt control register (AXIRERRCTL).
Page 117: Clock Pulse Generator
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Clock Pulse Generator This LSI has a clock pulse generator that generates a CPU clock (Iφ), internal bus clock (Bφ), peripheral clock 1 (P1φ), and peripheral clock 0 (P0φ). The clock pulse generator consists of a crystal oscillator, PLL circuits, and divider circuits. Features •...
Page 118 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Figure 6.1 shows a block diagram of the clock pulse generator. Divider 1 Divider 2 × 1 CPU clock × 1 PLL circuit (Iφ Max : 400.00 MHz) × 2/3 (×...
Page 119 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator The blocks of this module function as follows: (1) Crystal Oscillator A crystal oscillator is connected to the XTAL and EXTAL pins or to the USB_X2 and USB_X1 pins. Either the EXTAL or USB_X1 pin is selected by the clock mode settings.
Page 120: Input/Output Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Input/Output Pins Table 6.1 lists the clock pulse generator pins and their functions. Table 6.1 Pin Configuration and Functions of the Clock Pulse Generator Pin Name Symbol Function Mode control pin MD_CLK Input Switches between the EXTAL input and the USB_X1 input.
Page 121: Clock Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Clock Mode Table 6.2 indicates the input/output clock frequency. Table 6.3 shows the usable frequency ranges. Table 6.2 Input/Output Clock Frequency Mode Clock I/O MD_CLK Pin Setting Source Output Divider 1 PLL Circuit CKIO Frequency EXTAL/crystal...
Page 122 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator The clock source of the chip is switched by the setting of the MD_CLK pin while the RES pin is being held low. The following table shows the correspondence between clock source and pin settings. Table 6.4 Clock Source Selection MD_CLK Pin Setting...
Page 123: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Register Descriptions Table 6.6 shows the register configuration of the clock pulse generator. Table 6.6 Register Configuration Register Name Abbreviation Initial Value Address Access Size Frequency control FRQCR H'0335 H'FCFE0010 register 6.4.1 Frequency Control Register (FRQCR)
Page 124 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Initial Bit Name Value Description 5, 4 ― Reserved These bits are always read as 1. The write value should always be 1. ― Reserved This bit is always read as 0. The write value should always be 0. ―...
Page 125: Changing The Frequency
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Changing the Frequency The frequency of the CPU clock (Iφ) can be changed by changing the division rate of divider. The division rate can be changed by software through the frequency control register (FRQCR). 6.5.1 Changing the Division Ratio The division rate of divider can be changed by the following operation.
Page 126: Usage Of The Clock Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Usage of the Clock Pins For the connection of a crystal resonator or the input of a clock signal, this LSI circuit has the pins listed in Table 6.8. With regard to these pins, take care on the following points. Furthermore, Xin pin and Xout pin are used in this section to refer to the pins listed in the table.
Page 127: In The Case Of Using A Crystal Resonator
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator 6.6.2 In the Case of Using a Crystal Resonator An example of the connection of crystal resonator is shown in Figure 6.3. Place the crystal resonator and capacitors (CL1 and CL2) as close to pins Xin and Xout as possible. Furthermore, to avoid inductance so that oscillation is correct, use the points where the capacitors are connected to the crystal resonator in common and do not place wiring patterns close to these components.
Page 128: Oscillation Stabilizing Time
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Oscillation Stabilizing Time 6.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator In the case of using a crystal resonator, wait for the oscillation stabilizing time of the on-chip oscillation circuit at the following cases, to keep the oscillation stabilizing time of the on-chip crystal oscillator (in the case of inputting an external clock input, it is not necessary).
Page 129: Notes On Board Design
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Notes on Board Design 6.8.1 Note on Using a PLL Oscillation Circuit In the PLLVcc connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interferences.
Page 130: Definition Of Modulation Rate And Frequency In The Sscg Specification
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator Definition of Modulation Rate and Frequency in the SSCG Specification The SSCG circuit can be used to decrease the peak value of electromagnetic interference noise by frequency modulation, i.e. by slightly modulating the output frequency. In this case, the rate of change in the frequency and the size of the change to the input clock frequency are defined as the modulation rate and modulation frequency, respectively.
Page 131: Clock Signals
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator 6.10 Clock Signals 6.10.1 Clock Signals for the System and Realtime Clock Clock pulse generator Divider 1 Divider 2 PLL circuit CPU clock u 2/3 (u 30, 32) u 1/4 (II max.
Page 132: Audio And Usb Clock Signals
AUDIO_X2 oscillator AUDIO_XOUT AUDIO_X1 Serial sound interface channels 0 to 3 AUDIO_XOUT2 AUDIO_XOUT3 Oversampling Divider clock SCUX Renesas SPDIF Max. 50.00 MHz AUDIO_CLK Oversampling clock Channels 0 to 3 Divider Input Media local bus (RZ/A1L only) timing Max. 49.2544 MHz...
Page 133: Other Clock Signals
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator 6.10.4 Other Clock Signals CAN interface Peripheral 4.00 to 33.33 MHz Oversampling clock 1C clock CAN_CLK IEBus Controller (RZ/A1L only) Peripheral clock 0C Fixed to 32 MHz Debugger interface (CoreSight) Ethernet controller ET_TXCLK ET_RXCLK...
Page 134: Internal Clock Signals (1)
CD-ROM decoder (RZ/A1L only) SD host interface MMC host interface Serial sound interface, 4 channels SCUX Renesas serial peripheral interface, 3 channels Renesas SPDIF Media local bus (RZ/A1L only) Video display controller 5 JPEG codec unit (RZ/A1LU only) Internal buses (peripheral buses 3, 4, 5, and 7)
Page 135: Internal Clock Signals (2)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator 6.10.6 Internal Clock Signals (2) Module standby signals Serial communication interface with FIFO, 5 channels Peripheral clock 1C Serial communication interface, 2 channels (P1φ max. 66.67 MHz) CAN interface, 2 channels Internal bus (peripheral buses 3 and 4) Interrupt controller Direct memory access controller...
Page 136: Usage Note
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 6. Clock Pulse Generator 6.11 Usage Note 6.11.1 Notes on the SSCG When the SSCG is to be used, secure the SSCG stabilizing time (t ) shown in Table 47.5, Clock Timing in section SSCG 47, Electrical Characteristics.
Page 137: Interrupt Controller
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Interrupt Controller The interrupt controller ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The interrupt controller registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority.
Page 138: Input/Output Pins
Renesas SPDIF interface (Interrupt request) C bus interface (Interrupt request) Serial communication interface with FIFO (Interrupt request) CAN interface (Interrupt request) Renesas serial peripheral interface (Interrupt request) IEBus controller (RZ/A1L only) (Interrupt request) CD-ROM decoder (RZ/A1L only) (Interrupt request) MMC host interface...
Page 139: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Register Descriptions Table 7.2 shows the register configuration. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. For a description of the registers other than interrupt control register 0, interrupt control register 1, and IRQ interrupt ®...
Page 140 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt set-enable register 15 ICDISER15 H'00000000 H'E820113C Interrupt set-enable register 16 ICDISER16 H'00000000 H'E8201140 Interrupt clear-enable register 0 ICDICER0 H'00000000 H'E8201180 Interrupt clear-enable register 1...
Page 141 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt clear-pending register 9 ICDICPR9 H'00000000 H'E82012A4 Interrupt clear-pending register 10 ICDICPR10 H'00000000 H'E82012A8 Interrupt clear-pending register 11 ICDICPR11 H'00000000 H'E82012AC Interrupt clear-pending register 12...
Page 142 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt priority register 20 ICDIPR20 H'00000000 H'E8201450 Interrupt priority register 21 ICDIPR21 H'00000000 H'E8201454 Interrupt priority register 22 ICDIPR22 H'00000000 H'E8201458 Interrupt priority register 23...
Page 143 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt priority register 65 ICDIPR65 H'00000000 H'E8201504 Interrupt priority register 66 ICDIPR66 H'00000000 H'E8201508 Interrupt priority register 67 ICDIPR67 H'00000000 H'E820150C Interrupt priority register 68...
Page 144 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt priority register 110 ICDIPR110 H'00000000 H'E82015B8 Interrupt priority register 111 ICDIPR111 H'00000000 H'E82015BC Interrupt priority register 112 ICDIPR112 H'00000000 H'E82015C0 Interrupt priority register 113...
Page 145 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt processor target register 20 ICDIPTR20 H'00000000 H'E8201850 Interrupt processor target register 21 ICDIPTR21 H'00000000 H'E8201854 Interrupt processor target register 22 ICDIPTR22 H'00000000 H'E8201858...
Page 146 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt processor target register 65 ICDIPTR65 H'00000000 H'E8201904 Interrupt processor target register 66 ICDIPTR66 H'00000000 H'E8201908 Interrupt processor target register 67 ICDIPTR67 H'00000000 H'E820190C...
Page 147 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt processor target register 110 ICDIPTR110 H'00000000 H'E82019B8 Interrupt processor target register 111 ICDIPTR111 H'00000000 H'E82019BC Interrupt processor target register 112 ICDIPTR112 H'00000000 H'E82019C0...
Page 148 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.2 Register Configuration Access Register Name Abbreviation Initial Value Address Size Interrupt configuration register 20 ICDICFR20 H'55555555 H'E8201C50 Interrupt configuration register 21 ICDICFR21 H'55555555 H'E8201C54 Interrupt configuration register 22 ICDICFR22 H'55555555 H'E8201C58 Interrupt configuration register 23...
Page 149: Interrupt Control Register 0 (Icr0)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller 7.3.1 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. Bit: NMIL NMIE...
Page 150: Interrupt Control Register 1 (Icr1)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller 7.3.2 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. Bit: IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial value:...
Page 151: Irq Interrupt Request Register (Irqrr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller 7.3.3 IRQ Interrupt Request Register (IRQRR) IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F = 1 cancels the retained interrupts.
Page 152: Interrupt Sources
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Interrupt Sources There are four types of interrupt sources: NMI, IRQ, on-chip peripheral modules, and pin interrupts. Each interrupt has a priority level (0 to 31), with 0 the highest and 31 the lowest. 7.4.1 NMI Interrupt The NMI interrupt with the highest priority is accepted by the CPU as an FIQ exception all times.
Page 153: On-Chip Peripheral Module Interrupts
• Renesas SPDIF interface • I C bus interface • Serial communication interface with FIFO • CAN interface • Renesas serial peripheral interface • IEBus controller (RZ/A1L only) • CD-ROM decoder (RZ/A1L only) • MMC host interface • SD host interface •...
Page 154: Pin Interrupts
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller 7.4.4 Pin Interrupts Pin interrupts are input from pins TINT121 to TINT0. Signals input on pins TINT121 to TINT0 are conveyed as interrupt signals regardless of mode settings and pin function settings for the general-purpose I/O port pin. Accordingly, if pin interrupts are to be used in port mode, set the pin as an input port pin.
Page 155: Interrupt Ids
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Interrupt IDs Table 7.3 lists the interrupt sources and their interrupt IDs, and the registers for setting the interrupt sources. Do not make settings other than those in table 7.3, otherwise, the operation cannot be guaranteed. Each interrupt source is allocated a different interrupt ID.
Page 156 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level IRQ0 Level 1 to 0 7 to 0...
Page 157 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level Reserved 21 to 20 23 to 16 23 to 22...
Page 158 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level Reserved 1 to 0 7 to 0 3 to 2...
Page 159 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level Reserved 1 to 0 7 to 0 3 to 2...
Page 160 31 to 24 17 to 16 7 to 0 19 to 18 15 to 8 21 to 20 23 to 16 23 to 22 31 to 24 Renesas SPDIFI Level 25 to 24 7 to 0 SPDIF interface R01UH0437EJ0600 Rev.6.00 7-24...
Page 161 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level C bus INTIICTEI0 Level 27 to 26...
Page 162 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level Serial BRI0 Level 27 to 26...
Page 163 15 to 8 21 to 20 23 to 16 23 to 22 31 to 24 25 to 24 7 to 0 27 to 26 15 to 8 Renesas SPEI0 Level 29 to 28 23 to 16 serial SPRI0 Level 31 to 30...
Page 164 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level IEBus™ IEBBTD Edge 27 to 26...
Page 165 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level Media local MLB_CINT Level 11 to 10...
Page 166 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level Capture CEUI Level 25 to 24...
Page 167 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level Reserved 1 to 0 7 to 0 3 to 2...
Page 168 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level P1_6 TINT12 Edge/Level 25 to 24...
Page 169 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level P4_0 TINT48 Edge/Level 1 to 0...
Page 170 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level P6_8 TINT80 Edge/Level 1 to 0...
Page 171 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.3 List of Interrupt IDs Interrupt Source Register Allocation ICDISRn ICDISERn Interrupt ICDICERn Request Inter ICDISPRn Request Source Edge/ -rupt ICDICPRn ICDIPRn ICDABRn ICDICFRn ICDIPTRn Module Channel Name Level P8_4 TINT104 Edge/Level 17 to 16...
Page 172: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Operation 7.6.1 Initial Settings For details on the registers for making initial settings and the procedures for settings in general, see the Arm Generic ® Interrupt Controller Architecture Specification and the PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual from Arm.
Page 173 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Table 7.4 ICDICFRn Interrupt Configuration Register Settings Register Name Setting Interrupt ID ICDICFR0 H'AAAAAAAA 15 to 0 ICDICFR1 H'00000055 31 to 16 ICDICFR2 H'FFFD5555 47 to 32 ICDICFR3 H'555FFFFF 63 to 48 ICDICFR4 H'55555555 79 to 64...
Page 174: Flow Of Interrupt Operations
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller 7.6.2 Flow of Interrupt Operations For details on operation involved in interrupt generation, see the ArmGeneric Interrupt Controller Architecture ® Specification and the PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual from Arm. Figure 7.3 shows the flow of interrupt operations.
Page 175: Data Transfer With Interrupt Request Signals
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Data Transfer with Interrupt Request Signals Interrupt request signals can be used to activate the direct memory access controller and transfer data. Interrupt sources for which the direct memory access controller is designated as the destination by DMA extension resource selectors 0 to 7 are masked and requests from them are not input to the interrupt controller.
Page 176: Usage Note
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller Usage Note 7.8.1 Timing to Clear Interrupt Source Clear the interrupt source flag to 0 in the interrupt exception handler. It takes some time to clear an interrupt in the CPU after clearing the interrupt source flag to 0.
Page 177: Notes On Using Irq Pins As Triggers For Release From Standby When Software Standby Is In Use
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 7. Interrupt Controller 7.8.4 Notes on Using IRQ Pins as Triggers for Release from Standby when Software Standby is in Use To use an IRQ pin as the trigger for release from standby when software standby is in use, execute the following processing.
Page 178: Bus State Controller
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Bus State Controller The bus state controller outputs control signals for various types of memory and external devices that are connected to the external address space. The functions of this module enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.
Page 179 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Figure 8.1 shows a block diagram of this module. mastership CMNCR controller CS0WCR Wait WAIT controller CS5WCR TOSCOR0 TOSCOR5 TOSTR TOENR CS0BCR Area CS0 to CS5 controller CS5BCR A25 to A0, D31 to D0, BS, RD/WR, RD, WE3 to WE0...
Page 180: Input/Output Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Input/Output Pins Table 8.1 shows the pin configuration. Table 8.1 Pin Configuration Name Function A25 to A0 Output Address bus D31 to D0 Data bus Output Bus cycle start CS0 to CS5 Output Chip select RD/WR...
Page 181: Area Overview
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Area Overview 8.3.1 Address Map In the architecture, this LSI has a 32-bit address space, which is divided into external memory spaces (SPI multi I/O bus space, large-capacity on-chip RAM, hold on-chip RAM, on-chip peripheral modules, and reserved areas) according to the upper bits of the address.
Page 182: Data Bus Width And Related Pin Setting For Each Area Depending On Boot Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.3.2 Data Bus Width and Related Pin Setting for Each Area Depending on Boot Mode The initial state of data bus width and settings of the pins related to this module depends on boot mode. For boot mode, refer to section 3, Boot Mode.
Page 183: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Register Descriptions Table 8.4 shows the register configuration of this module. Do not access the areas until settings of the connected memory interface are completed. Table 8.4 Register Configuration Register Name Abbreviation Initial Value Address...
Page 184: Common Control Register (Cmncr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. Bit: Initial value: R/W: Bit: DPRTY[1:0] CNT* Initial value: R/W: Initial Bit Name Value Description 31 to 29...
Page 185: Csn Space Bus Control Register (Csnbcr) (N = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 5) CSnBCR is a 32-bit readable/writable register that specifies the memory connected to each space, the number of idle cycles between bus cycles, and the bus width.
Page 186 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description 21 to 19 IWRRD[2:0] Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space.
Page 187: Csn Space Wait Control Register (Csnwcr) (N = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 5) CSnWCR specifies various wait cycles for memory access. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR).
Page 188 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description 10 to 7 WR[3:0] 1010 Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles...
Page 189 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller • CS1WCR Bit: WW[2:0] Initial value: R/W: Bit: SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: Initial Bit Name Value Description 31 to 21 ― All 0 Reserved These bits are always read as 0. The write value should always be 0. SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used.
Page 190 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description 10 to 7 WR[3:0] 1010 Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles...
Page 191 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller • CS2WCR, CS3WCR Bit: Initial value: R/W: Bit: WR[3:0] Initial value: R/W: Initial Bit Name Value Description 31 to 21 ― All 0 Reserved These bits are always read as 0. The write value should always be 0. SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used.
Page 192 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller • CS4WCR Bit: WW[2:0] Initial value: R/W: Bit: SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: Initial Bit Name Value Description 31 to 21 ― All 0 Reserved These bits are always read as 0. The write value should always be 0. SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used.
Page 193 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description 10 to 7 WR[3:0] 1010 Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles...
Page 194 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller • CS5WCR Bit: MPXW/ SZSEL WW[2:0] Initial value: R/W: Bit: SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: Initial Bit Name Value Description 31 to 22 ― All 0 Reserved These bits are always read as 0. The write value should always be 0. SZSEL MPX-I/O Interface Bus Width Specification Specifies an address to select the bus width when the BSZ[1:0] of...
Page 195 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description 12, 11 SW[1:0] Number of Delay Cycles from Address, CS5 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS5 assertion to RD and WEn assertion when area 5 is specified as normal space or SRAM with byte selection.
Page 196 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (2) Burst ROM (Clocked Asynchronous) • CS0WCR Bit: BST[1:0] BW[1:0] Initial value: R/W: Bit: W[3:0] Initial value: R/W: Initial Bit Name Value Description 31 to 22 ― All 0 Reserved These bits are always read as 0.
Page 197 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0...
Page 198 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller • CS4WCR Bit: BST[1:0] BW[1:0] Initial value: R/W: Bit: SW[1:0] W[3:0] HW[1:0] Initial value: R/W: Initial Bit Name Value Description 31 to 22 ― All 0 Reserved These bits are always read as 0. The write value should always be 0. 21, 20 BST[1:0] Burst Count Specification...
Page 199 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description 10 to 7 W[3:0] 1010 Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles...
Page 200 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (3) SDRAM* • CS2WCR Bit: Initial value: R/W: Bit: A2CL[1:0] Initial value: R/W: Initial Bit Name Value Description 31 to 11 ― All 0 Reserved These bits are always read as 0. The write value should always be 0. ―...
Page 201 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller • CS3WCR Bit: Initial value: R/W: Bit: WTRP[1:0]* WTRCD[1:0]* A3CL[1:0] TRWL[1:0]* WTRC[1:0]* Initial value: R/W: Note: If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common.
Page 202 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description 4, 3 TRWL[1:0]* Number of Auto-Precharge Startup Wait Cycles Specify the number of minimum auto-precharge startup wait cycles as shown below. • Cycle number from the issuance of the WRITA command by this LSI until the completion of auto-precharge in the SDRAM.
Page 203 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (4) Burst ROM (Clocked Synchronous) • CS0WCR Bit: BW[1:0] Initial value: R/W: Bit: W[3:0] Initial value: R/W: Initial Bit Name Value Description 31 to 18 ― All 0 Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] Number of Burst Wait Cycles...
Page 204: Sdram Control Register (Sdcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.4 SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. Bit: A2ROW[1:0] A2COL[1:0] Initial value: R/W: Bit: DEEP RFSH RMODEPDOWN BACTV A3ROW[1:0] A3COL[1:0]...
Page 205 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description PDOWN Power-Down Mode Specifies whether the SDRAM will enter the power-down mode after the access to the SDRAM. With this bit being set to 1, after the SDRAM is accessed, the CKE signal is driven low and the SDRAM enters the power- down mode.
Page 206: Refresh Timer Control/Status Register (Rtcsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is adjusted only by a power-on reset.
Page 207: Refresh Timer Counter (Rtcnt)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS[2:0] in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection.
Page 208: Timeout Cycle Constant Register (Toscorn) (N = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.8 Timeout Cycle Constant Register (TOSCORn) (n = 0 to 5) TOSCORn is a 16-bit register the value of which is effective when the WM bit in the CSn space wait control register (CSnWCR) is 0 and the corresponding bit in the timeout enable register (TOENR) is 1.
Page 209: Timeout Status Register (Tostr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.9 Timeout Status Register (TOSTR) TOSTOR is an 8-bit register that holds the timeout status flags for the CS spaces. When the WM bit in the CSn space wait control register (CSnWCR) is 0 and the corresponding bit in the timeout enable register (TOENR) is 1 and the number of cycles of waiting in response to the signal on the eternal wait input matches the setting of TOSCORn, the timeout status flag for the corresponding space is set and a timeout detection interrupt request is generated.
Page 210 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Initial Bit Name Value Description CS0TOSTF CS0 Space Timeout Status Flag Status flag that indicates that the number of cycles of waiting due to the input on the external wait pin during access to the CS0 space has matched the setting of the CS0 space timeout cycle constant register (TOSCOR0).
Page 211: Timeout Enable Register (Toenr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.4.10 Timeout Enable Register (TOENR) TOENR is an 8-bit register that specifies enabling or disabling the detection of timeout for waiting in each of the CS spaces. Bit: Initial value: R/W: Bit: TOEN...
Page 212: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Operation 8.5.1 Access Size and Data Alignment This LSI supports little endian, in which the least significant byte (LSB) is that in the direction of the 0th address. Data bus width can be selected from 8 bits, 16 bits, and 32 bits for the normal memory and SRAM with byte selection. Data bus width can be selected from 16 bits and 32 bits for SDRAM.
Page 213 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.6 16-Bit External Device Access and Data Alignment in Little Endian Data Bus Strobe Signals D31 to D23 to D15 to WE3, WE2, WE1, WE0, Operation D7 to D0 DQMUU DQMUL DQMLU...
Page 214: Normal Space Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.2 Normal Space Interface (1) Basic Timing For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see section 8.5.8, SRAM Interface with Byte Selection.
Page 215 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device. 16 bits are always read in case of a 16-bit device.
Page 216 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO A25 to A0 RD/WR Read D15 to D0 Write D15 to D0 DACKn WAIT Note: The waveform for DACKn is when active low is specified. Figure 8.4 Continuous Access to Normal Space (2) Bus Width = 16 Bits, 32-Bit Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) R01UH0437EJ0600 Rev.6.00 8-39...
Page 217 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 128K × 8-bit This LSI SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 8.5 Example of 32-Bit Data-Width SRAM Connection R01UH0437EJ0600 Rev.6.00 8-40 Jan 29, 2021...
Page 218 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 128K × 8-bit This LSI SRAM I/O7 I/O0 I/O7 I/O0 Figure 8.6 Example of 16-Bit Data-Width SRAM Connection 128K × 8-bit This LSI SRAM I/O7 I/O0 Figure 8.7 Example of 8-Bit Data-Width SRAM Connection R01UH0437EJ0600 Rev.6.00 8-41 Jan 29, 2021...
Page 219: Access Wait Control
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 1, 4, and 5 to insert wait cycles independently in read access and in write access. Areas 0, 2, and 3 have common access wait for read cycle and write cycle.
Page 220 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in Figure 8.9. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle.
Page 221: Csn Assert Period Expansion
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.4 CSn Assert Period Expansion The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0.
Page 222: Mpx-I/O Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.5 MPX-I/O Interface Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WEn signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space.
Page 223 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO A25 to A0 RD/WR Read Address Data D15/D7 to D0 Write D15/D7 to D0 Address Data DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.11 (2) Access Timing for MPX Space (Address Cycle No Wait, Extended Assertion Cycle 1.5, Data Cycle No Wait, Extended Negation Cycle 1.5)
Page 224 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Tadw CKIO A25 to A0 RD/WR Read Address Data D15/D7 to D0 Write D15/D7 to D0 Address Data DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait) Tadw...
Page 225: Sdram Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.6 SDRAM Interface (1) SDRAM Direct Connection The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles.
Page 226 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Figure 8.14 and Figure 8.15 show examples of the connection of the SDRAM with the LSI. 64M SDRAM (1M × 16-bit × 4-bank) This LSI CKIO RD/WR I/O15 I/O0 DQMU DQMUU DQML DQMUL...
Page 227 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (2) Address Multiplexing An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR and bits A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR.
Page 228 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.8 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-2 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 11 (32 bits) 01 (12 bits) 00 (8 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 229 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.9 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-1 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 230 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.9 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 231 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.10 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3) Setting A2/3 A2/3 [1:0] [1:0] [1:0] 11 (32 bits) 10 (13 bits) 01 (9 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 232 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-1 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 233 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-2 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 234 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-1 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 235 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-2 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 236 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.13 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-1 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 237 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.13 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-2 Setting A2/3 A2/3 [1:0] [1:0] [1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) Output Pin of This Row Address Output Column Address Output Cycle...
Page 238 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (3) Burst Read A burst read occurs in the following cases with this LSI. • Access size in reading is larger than data bus width. • 16-, 32- or 64-byte transfer This LSI always accesses the SDRAM with burst length 1.
Page 239 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (Tap) CKIO A25 to A0 A12/A11* RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.16 Burst Read Basic Timing (CAS Latency 1, Auto Pre-Charge) (Tap)
Page 240 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (4) Single Read A read access ends in one cycle when the data bus width is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst length 1, only the required data is output. A read access that ends in one cycle is called single read.
Page 241 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (5) Burst Write A burst write occurs in the following cases in this LSI. • Access size in writing is larger than data bus width. • 16-, 32- or 64-byte transfer This LSI always accesses SDRAM with burst length 1.
Page 242 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (6) Single Write A write access ends in one cycle when the data bus width is larger than or equal to access size. As a single write or burst write with burst length 1 is set in SDRAM, only the required data is output. The write access that ends in one cycle is called single write.
Page 243 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (7) Bank Active The SDRAM bank function can be used to support high-speed access to the same row address. When the BACTV bit in SDCR is 1, access is performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function.
Page 244 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO A25 to A0 A12/A11* RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.21 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1) Tnop...
Page 245 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO A25 to A0 A12/A11* RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.23 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) CKIO...
Page 246 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Tnop CKIO A25 to A0 A12/A11* RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.25 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank) CKIO...
Page 247 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (8) Refreshing This module has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR.
Page 248 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (b) Self-refreshing Self-refresh mode is a kind of standby mode, in which the refresh timing and refresh addresses are generated within the SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank.
Page 249 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (9) Relationship between Refresh Requests and Bus Cycles If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval must be prevented from occurring.
Page 250 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller (11) Power-On Sequence In order to use SDRAM, mode setting must first be made for SDRAM after the pose interval specified for the SDRAM to be used after powering on. The pose interval should be obtained by a power-on reset generating circuit or software. To perform SDRAM initialization correctly, the registers of this module must first be set, followed by a write to the SDRAM mode register.
Page 251 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Mode register setting timing is shown in Figure 8.30. A PALL command (all bank pre-charge command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued.
Page 252 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.16 Output Addresses when EMRS Command Is Issued Write Access MRS Command EMRS Command Command to be Issued Access Address Access Data Size Issue Address Issue Address CS2 MRS H'3FFFDXX0 H'******** 16 bits...
Page 253 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Tdpd CKIO A25 to A0 A12/A11* RD/WR DQMxx Hi-Z D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.32 Deep Power-Down Mode Transition Timing R01UH0437EJ0600 Rev.6.00...
Page 254: Burst Rom (Clocked Asynchronous) Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.7 Burst ROM (Clocked Asynchronous) Interface The burst ROM (clocked asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM (clocked asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent access cycles are performed only by changing the address, without negating the RD signal at the end of the 1st cycle.
Page 255: Sram Interface With Byte Selection
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO A25 to A0 RD/WR D31 to D0 WAIT DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.33 Burst ROM Access Timing (Clocked Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1) 8.5.8...
Page 256 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO A25 to A0 RD/WR Read D31 to D0 RD/WR High Write D31 to D0 DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.34 Basic Access Timing for SRAM with Byte Selection (BAS = 0) R01UH0437EJ0600 Rev.6.00 8-79...
Page 257 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO A25 to A0 RD/WR Read D31 to D0 RD/WR High Write D31 to D0 DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.35 Basic Access Timing for SRAM with Byte Selection (BAS = 1) R01UH0437EJ0600 Rev.6.00 8-80...
Page 258 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO A25 to A0 RD/WR Read D31 to D0 RD/WR High Write D31 to D0 DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.36 Wait Timing for SRAM with Byte Selection (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01) R01UH0437EJ0600 Rev.6.00 8-81...
Page 259 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 64K × 16-bit SRAM This LSI RD/WR I/O15 I/O0 I/O15 I/O0 Figure 8.37 Example of Connection with 32-Bit Data-Width SRAM with Byte Selection 64K × 16-bit This LSI SRAM RD/WR I/O 15 I/O 0 Figure 8.38...
Page 260: Burst Rom (Clocked Synchronous) Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.9 Burst ROM (Clocked Synchronous) Interface The burst ROM (clocked synchronous) interface is supported to access a ROM with a synchronous burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as a normal space. This interface is valid only for area 0.
Page 261: Wait Between Access Cycles
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.10 Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur.
Page 262 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller Table 8.18 Conditions for Determining Number of Idle Cycles Condition Description Range Note IW***[2:0] in These bits specify the number of idle cycles for 0 to 12 Do not set 0 for the number of idle CSnBCR access.
Page 263 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller CKIO External bus idle cycles Previous access Next access Idle cycle after access Idle cycle before access [1] IW***[2:0] setting in CSnBCR Condition [1] [2] WTRP[1:0] setting in CSnWCR TRWL[1:0] setting in CSnWCR Either one of them Condition [2] or [3] WTRC[1:0] setting in CSnWCR...
Page 264: Others
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 8. Bus State Controller 8.5.11 Others (1) Reset This module can be initialized completely only at power-on reset. At power-on reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state after the internal reset is synchronized with the internal clock.
Page 265: Direct Memory Access Controller
CD-ROM decoder: 1 source (RZ/A1L only) — SD host interface: 4 sources — MMC host interface: 2 sources — Renesas serial peripheral interface: 6 sources — IEBus™ controller: 2 sources (RZ/A1L only) — OS timer: 2 sources — SCUX: 8 sources —...
Page 266: Input/Output Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller • Interval: A specific DMA transfer interval can be specified to adjust the bus occupancy. Input/Output Pins Table 9.1 lists the pin configuration. This module has pins for a single channel (CH0) as the external bus use. Table 9.1 Pin Configuration Channel...
Page 267 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller It consists of the Next0 Register Set and the Next1 Register Set. In register mode, set this register set by using software. In link mode, the descriptor read data is automatically set in the Next0 Register Set.
Page 268: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Register Descriptions Table 9.2 lists the register configuration. There are eleven control registers and five status registers for each channel, and twelve common control registers are used by all channels. In addition, there is one extension resource selector per two channels.
Page 269 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Next0 source address register 2 N0SA_2 H'00000000 H'E8200080 Next0 destination address register 2 N0DA_2 H'00000000 H'E8200084 Next0 transaction byte register 2 N0TB_2 H'00000000...
Page 270 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Next0 source address register 4 N0SA_4 H'00000000 H'E8200100 Next0 destination address register 4 N0DA_4 H'00000000 H'E8200104 Next0 transaction byte register 4 N0TB_4 H'00000000...
Page 271 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Next0 source address register 6 N0SA_6 H'00000000 H'E8200180 Next0 destination address register 6 N0DA_6 H'00000000 H'E8200184 Next0 transaction byte register 6 N0TB_6 H'00000000...
Page 272 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Next0 source address register 8 N0SA_8 H'00000000 H'E8200400 Next0 destination address register 8 N0DA_8 H'00000000 H'E8200404 Next0 transaction byte register 8 N0TB_8 H'00000000...
Page 273 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Next0 source address register 10 N0SA_10 H'00000000 H'E8200480 Next0 destination address register 10 N0DA_10 H'00000000 H'E8200484 Next0 transaction byte register 10 N0TB_10 H'00000000...
Page 274 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Next0 source address register 12 N0SA_12 H'00000000 H'E8200500 Next0 destination address register 12 N0DA_12 H'00000000 H'E8200504 Next0 transaction byte register 12 N0TB_12 H'00000000...
Page 275 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Next0 source address register 14 N0SA_14 H'00000000 H'E8200580 Next0 destination address register 14 N0DA_14 H'00000000 H'E8200584 Next0 transaction byte register 14 N0TB_14 H'00000000...
Page 276: Next Source Address Register N (N0Sa_N, N1Sa_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.1 Next Source Address Register n (N0SA_n, N1SA_n) This register sets the DMA transfer source address (32 bits) of DMA channel n (n = 0 to 15) which is to be executed next. N0SA_n is for the Next0 Register Set, and N1SA_n is for the Next1 Register Set.
Page 277: Next Transaction Byte Register N (N0Tb_N, N1Tb_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.3 Next Transaction Byte Register n (N0TB_n, N1TB_n) This register sets the total transfer byte count (DMA transaction) of DMA channel (n = 0 to 15) which is to be executed next.
Page 278: Current Destination Address Register (Crda_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.5 Current Destination Address Register (CRDA_n) This register indicates the DMA transfer destination address of DMA channel n (n = 0 to 15). The values are loaded from the Next0/1 Register Set in register mode or from the descriptor read data in link mode. You cannot write to this register set using software.
Page 279: Channel Status Register N (Chstat_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.7 Channel Status Register n (CHSTAT_n) This register indicates the status of DMA channel n (n = 0 to 15). Bit: INTMSK Initial value: R/W: Bit: MODE TACT RQST Initial value: R/W: Initial...
Page 280 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Initial Bit Name Value Description Descriptor Load Indicates whether the descriptor is being loaded. The bit maintains 1 if a bus error is received during descriptor load. 0: Operation other than descriptor load 1: (ER = 0) Descriptor load is in progress in link mode.
Page 281 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Initial Bit Name Value Description Suspend Indicates whether the channel is suspended. 0: Channel_n not suspended 1: Channel_n suspended Set condition(s): • When SETSUS (CHCTRL_n) is set to 1 during a DMA transfer on Channel_n, creating a SUSPEND status internally Clear condition(s): •...
Page 282: Channel Control Register N (Chctrl_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.8 Channel Control Register n (CHCTRL_n) This register controls the DMA transfer operation on DMA channel n (n = 0 to 15). Bit: CLRINT SETINT Initial value: R/W: Bit: CLRTC CLRRQ SWRST STG CLREN SETEN...
Page 283 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Initial Bit Name Value Description SWRST Software Reset Setting this bit to 1 can clear the channel status register (CHSTAT_n). When setting this bit to 1, make sure that both the EN bit and TACT bit are set to 0. An attempt to read this bit results in 0 being read.
Page 284: Channel Configuration Register N (Chcfg_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.9 Channel Configuration Register n (CHCFG_n) This register controls the DMA transfer operation on DMA channel n (n = 0 to 15). Bit: RSEL DDS[3:0] Initial value: R/W: Bit: SDS[3:0] AM[2:0] HIEN...
Page 285 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Initial Bit Name Value Description Transfer Mode Sets the DMA transfer mode. 0: Single transfer mode (initial value) 1: Block transfer mode Sets the destination address counting direction of DMA channel n. 0: Increment (initial value) 1: Fixed Sets the source address counting direction of DMA channel n.
Page 286: Channel Interval Register N (Chitvl_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Initial Bit Name Value Description HIEN High Enable Selects whether to detect a DMA request using the High level or rising edge of the signal. When LVL = 0: HIEN = 1: Detects a request in response to the rising edge of the signal.
Page 287: Channel Extension Register N (Chext_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.11 Channel Extension Register n (CHEXT_n) This is an extension register for DMA channel n (n = 0 to 15). Bit: Initial value: R/W: Bit: DCA[3:0] DPR[2:0] SCA[3:0] SPR[2:0] Initial value: R/W: Initial...
Page 288: Next Link Address Register N (Nxla_N)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.12 Next Link Address Register n (NXLA_n) This is a 32-bit register that sets the link address of DMA channel n (n = 0 to 15). For information about the link mode, see section 9.6.3, Link Mode. Bit: NXLA Initial value:...
Page 289: Dma Control Register (Dctrl_0_7, Dctrl_8_15)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.14 DMA Control Register (DCTRL_0_7, DCTRL_8_15) This register sets the transfer type for descriptor access and the arbitration between channels. (DCTRL_0_7 is common for channels 0 to 7 and DCTRL_8_15 is common for channels 8 to 15.) Bit: LWCA LWPR...
Page 290: Dma Status En Register (Dstat_En_0_7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.15 DMA Status EN Register (DSTAT_EN_0_7) This register indicates the EN bit status of the CHSTAT_n register (n = 0 to 7). Even if you write to this register, the values of the individual bits do not change. Bit: Initial value: R/W:...
Page 291: Dma Status Er Register (Dstat_Er_0_7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.17 DMA Status ER Register (DSTAT_ER_0_7) This register indicates the ER bit status of the CHSTAT_n register (n = 0 to 7). Even if you write to this register, the values of the individual bits do not change. Bit: Initial value: R/W:...
Page 292: Dma Status End Register (Dstat_End_0_7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.19 DMA Status END Register (DSTAT_END_0_7) This register indicates the END bit status of the CHSTAT_n register (n = 0 to 7). Even if you write to this register, the values of the individual bits do not change. Bit: Initial value: R/W:...
Page 293: Dma Status Tc Register (Dstat_Tc_0_7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.21 DMA Status TC Register (DSTAT_TC_0_7) This register indicates the TC bit status of the CHSTAT_n register (n = 0 to 7). Even if you write to this register, the values of the individual bits do not change. Bit: Initial value: R/W:...
Page 294: Dma Status Sus Register (Dstat_Sus_0_7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.4.23 DMA Status SUS Register (DSTAT_SUS_0_7) This register indicates the SUS bit status of the CHSTAT_n register (n = 0 to 7). Even if you write to this register, the values of the individual bits do not change. Bit: Initial value: R/W:...
Page 295: Dma Extension Resource Selectors 0 To 7 (Dmars0 To Dmars7)
Renesas SPDIF interface: 2 sources CD-ROM decoder: 1 source (RZ/A1L only) SD host interface: 4 sources MMC host interface: 2 sources Renesas serial peripheral interface: 6 sources IEBus™ controller: 2 sources (RZ/A1L only) OS timer: 2 sources SCUX: 8 sources...
Page 296 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller • DMARS0 Bit: CH1 MID[6:0] CH1 RID[1:0] Initial value: R/W: Bit: CH0 MID[6:0] CH0 RID[1:0] Initial value: R/W: • DMARS1 Bit: CH3 MID[6:0] CH3 RID[1:0] Initial value: R/W: Bit: CH2 MID[6:0] CH2 RID[1:0] Initial value:...
Page 297 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller • DMARS4 Bit: CH9 MID[6:0] CH9 RID[1:0] Initial value: R/W: Bit: CH8 MID[6:0] CH8 RID[1:0] Initial value: R/W: • DMARS5 Bit: CH11 MID[6:0] CH11 RID[1:0] Initial value: R/W: Bit: CH10 MID[6:0] CH10 RID[1:0] Initial value:...
Page 298: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request.
Page 299 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.3 Settings for External Request Detection CHCFG_0 HIEN LOEN Detection of External Request Falling edge detection Rising edge detection Low level detection High level detection When DREQ0 is accepted, the DREQ0 pin enters the request accept disabled state (non-sensitive period). After issuing an acknowledge DACK0 signal for the accepted DREQ0, the DREQ0 pin again enters the request accept enabled state.
Page 300 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.4 On-Chip Peripheral Module Requests DMARS CHCFG_n DMA Transfer DMA Transfer Transfer Transfer Request Source Request Signal Source Destination [2:0] HIEN SEL[2:0] Serial TXI3 Arbitrary SCFTDR_3 001_1011 Ch0: 000 communication (transmit empty) Ch1: 001...
Page 301 (FFD0_2 request) SCURXI2 DMATU2_CI Arbitrary (FFU0_2 request) SCUTXI3 Arbitrary DMATD3_CI 100_0011 (FFD0_3 request) SCURXI3 DMATU3_CI Arbitrary (FFU0_3 request) Renesas serial SPTI0 Arbitrary SPDR_0 100_1000 peripheral interface (transmit data channel 0 empty) SPRI0 SPDR_0 Arbitrary (receive data full) Renesas serial SPTI1...
Page 302 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.4 On-Chip Peripheral Module Requests DMARS CHCFG_n DMA Transfer DMA Transfer Transfer Transfer Request Source Request Signal Source Destination [2:0] HIEN SEL[2:0] Serial TXI0 Arbitrary TDR0 101_1010 Ch0: 000 communication Ch1: 001 RXI0...
Page 303: Dma Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller DMA Mode 9.6.1 Mode Setting You can toggle between register mode and link mode, by using the DMS field of the CHCFG_n register. Table 9.5 DMA Mode Setting (CHCFG_n) Mode Description Register mode...
Page 304 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller The above figure shows how the transfer is executed when the Next0 Register Set is used (upper part of the figure) and when the Next1 Register Set is used (lower part of the figure). (1) Operation Flow Setup by software Set channel...
Page 305 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller <Explanation of the register mode flow> 1. Channel setting (set channel configuration) The Next0 or Next1 Register Set (destination address, source address, and total transfer byte count) is set. In the Channel Register Set, the DMA Register Set (REQ, DMAACK, transfer size, etc.) is set.
Page 306 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (2) Register Setting (a) Register mode setting Select the register set to be executed. Table 9.6 Register Mode Setting RSEL (CHCFG_n) (CHCFG_n) Description Executes the Next0 Register Set. Executes the Next1 Register Set. (b) DMA transfer end interrupt mask setting The DMA transfer end interrupt can be masked individually for each register set.
Page 307 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (d) Automatic register set change setting When 1 is set in REN, the DMAC can automatically change to the register set to be executed next, after a DMA transaction is completed. Table 9.9 Automatic Register Set Change Setting (CHCFG_n)
Page 308 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (b) When two register sets are used continuously Table 9.11 Automatic Register Set Execution Setting RSEL (CHCFG_n) (CHCFG_n) (CHCFG_n) (CHCFG_n) (CHCFG_n) (Register mode) (Next0) (masked) (switched) (continuously executed) 6.DMAEND Next0 Register Set Source Address Current Register Set...
Page 309: Link Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.6.3 Link Mode In link mode, a descriptor stored in external memory is loaded as set values and a DMA transaction is executed using the loaded values. The DMAC contains a Next Link address and a Current Link address for each channel, and these addresses are used to set the descriptor address to be executed next and to indicate the descriptor address of the currently executed DMA transaction, respectively.
Page 310 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (1) Operation Flow Set up by software Processing by hardware Bus transaction Set channel enable Set link address SETEN = 1 Reflect descriptor data to registers Update link Update registers address Update current link address NXLA ->...
Page 311 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller <Explanation of the link mode flow> 1. Channel setting The start address of the link destination is set in NXLA_n. 2. Link address update When 1 is set in EN (1 is set in SETEN), the Link address set in NXLA_n is loaded to CRLA_n. 3.
Page 312 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (2) Register Setting (a) Link mode setting To use the link mode, set 1 in the DMS bit of the CHCFG_n register. Table 9.12 Link Mode Setting (CHCFG_n) Description Operates in link mode.
Page 313 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (b) header The header indicates the status of the descriptor, as shown below. The DMAC reads this area when a DMA transfer is started in link mode. Also, after a DMA transaction is completed, the DMAC writes back the transfer status to the area.
Page 314 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (e) Descriptor area and DMA transfer area The following figure outlines the descriptor area and DMA transfer area that are accessed by the DMAC. External memory or on-chip memory space [31:0] header descriptor 1...
Page 315 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 4 through 6 are repeated. When the header contains 1 in LE and 0 in WBD, the DMAC executes a DMA transfer using the settings of that descriptor, writes back data with 0 set in the LV bit of the header and ends the operation. When the header contains 1 in both LE and WBD, the DMAC executes a DMA transfer using the settings of that descriptor and ends the operation (without writing back).
Page 316: Dma Transfer
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller DMA Transfer The basic operation of DMA transfer is described here. 9.7.1 Transfer Mode Two transfer modes are supported: single transfer mode and block transfer mode. To select a transfer mode, set the TM bit of CHCFG_n for each channel. Table 9.16 Basic Transfer Setting Transfer Mode...
Page 317: Priority Control For Dma Channels
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.7.2 Priority Control for DMA Channels Within channels 0 to 7 and 8 to 15, two priority control modes are supported: fixed priority mode and round robin mode. Only round robin mode is supported for priority control between the group of channels 0 to 7 and the group of channels 8 to 15.
Page 318 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (2) Round Robin Mode In round robin mode, each time a transfer request is received from a channel in the group of channels 0 to 7 and the group of channels 8 to 15, the order of priority is changed in such a way that the channel that executed a transfer last has the lowest priority.
Page 319: Number Of States Of An External Bus Cycle
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.7.3 Number of States of an External Bus Cycle When this module is the bus master, the number of states of an external bus cycle is controlled by the bus state controller as when the CPU is the bus master.
Page 320 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller CKIO DREQ0 Internal request DACK0 DMA Transfer Read Write Read Figure 9.16 Edge Detection Timing (HIEN = 1, REQD = 1) (2) Level Detection Setting 1 in the LVL bit of the CHCFG_n register enables level detection. DREQ0 is regarded as valid when it remains active for two consecutive clock cycles or more (depending on the HIEN and LOEN settings).
Page 321: Dma Acknowledge Output Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.7.5 DMA Acknowledge Output Function DACK0 is an acknowledge signal that is sent to DREQ0. Level output and bus cycle output settings are supported as the DACK0 output mode. DACK0 is asserted at the same time as CS assertion except for the MPX-IO interface. For details, refer to section 8, Bus State Controller.
Page 322 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller CKIO CHCFG_n.AM[2:0] CHCFG_n.REQD DREQ0 Internal request DACK0 DMA Transfer Read Write Figure 9.20 DACK0 Output Timing (AM[2:0] = 001, REQD = 1) (3) Bus Cycle Output Setting 010 in the AM bits of the CHCTRL_n register enables bus cycle output. DACK0 remains active for the duration of a bus cycle.
Page 323: Dma Transfer End Output Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller • In the write active mode (REQD = 1), DACK0 remains active from the time when a write request is output until one cycle after the response to the final data is returned. •...
Page 324: Dma Error Interrupt
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.7.8 DMA Error Interrupt If an error response is received for a DMA transfer or descriptor access, the DMAC regards it as an error and stops the transfer. Upon receiving an error response, the EN bit of the CHSTAT_n register of transferring channel n is cleared to 0 and 1 is set in the ER bit (n = 0 to 15).
Page 325: Difference In Operation Due To The Transfer Size
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.7.10 Difference in Operation Due to the Transfer Size (1) When the Source Transfer Size Is Smaller When the read of data equivalent to the destination data size is completed, the data is written to the destination. The following figure shows a timing chart where the source transfer size is 8 bits and the destination transfer size is 32 bits (in the case of rising edge detection).
Page 326: Transfer Status
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (3) When the Source Transfer Size Is the Same as the Destination Transfer Size Every time a DMA transfer request is detected, a source read and a destination write occur. The following figure shows a timing chart where the source transfer size and the destination transfer size are both 8 bits (in the case of rising edge detection, with 1 set in REQD of the CHCFG_n register).
Page 327 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (2) Transfer Stop If you write 1 to CLREN while a DMA transaction is in progress, you can stop the DMA transaction for the corresponding channel. For the post-stop processing, two modes are supported: one sweeps out the data remaining in the buffer when the transaction is stopped (SBE = 1) and the other does not (SBE = 0).
Page 328 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller (b) Transfer Stop (Buffer Sweep Enabled - SBE = 1) If 1 is set in CLREN during a DMA transfer, the DMA transfer is stopped. When 0 is set in REQD, the DMA transfer is stopped after the DMAC sweeps (writes) the already read data.
Page 329 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Suspend Start (transfer stop) Set 1 in SETSUS of CHCTRL_n Read CHSTAT_n Repeat polling until SUS is set to 1 EN = 1 SUS = 1 Set 1 in CLREN of CHCTRL_n SBE = 1 Sweep...
Page 330: Dma Setting Examples
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller DMA Setting Examples Setting examples applicable when DMA transfer is executed using the direct memory access controller are shown in the following. The transfer conditions for these setting examples are as follows. Table 9.21 Transfer Condition List for DMA Transfer Setting Examples DMA Mode...
Page 331 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Start (setting example 1) ⋅ Fixed priority DCTRL ← 00000000H N0SA_3 ← 11110000H ⋅ Source: 1111000H N0DA_3 ← 22220000H ⋅ Destination: 22220000H N0TB_3 ← 00000040H ⋅ Transfer size: 64 bytes CHCFG_3 ←...
Page 332: Setting Example 2 (Register Mode/Software Request)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.8.2 Setting Example 2 (Register Mode/Software Request) The following table shows a setting example applicable when DMA transfer is executed using the settings shown below. Table 9.23 DMA Transfer Setting Example 2 Item Description Channel used...
Page 333 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Start (setting example 2) ⋅ Round robin DCTRL ← 00000001H N1SA_2 ← 0FFFE000H ⋅ Source: 0FFFE000H N1DA_2 ← 33330000H ⋅ Destination: 33330000H N1TB_2 ← 00000080H ⋅ Transfer size: 128 bytes CHCFG_2 ←...
Page 334: Setting Example 3 (Register Mode/Continuous Execution)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.8.3 Setting Example 3 (Register Mode/Continuous Execution) The following table shows a setting example applicable when DMA transfer is executed using the settings shown below. Table 9.24 DMA Transfer Setting Example 3 Item Description Channel used...
Page 335: Setting Example 4 (Link Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Start (setting example 3) ⋅ Round robin DCTRL ← 00000001H ⋅ Source: N0SA_1 ← 11110000H 11110000H ⋅ Destination: 33330000H N0DA_1 ← 33330000H ⋅ Transfer size: 512 bytes N0TB_1 ← 00000200H ⋅...
Page 336 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.26 DMA Transfer Setting Example 4 (Descriptor 1) Item Description Descriptor start address 0000_1000H Next descriptor start address 0000_2000H Transfer mode Block transfer Next0 Source Destination Start address 1111_0000H 3333_0000H Address direction...
Page 337 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Table 9.28 DMA Transfer Setting Example 4 (Descriptor 3) Item Description Descriptor start address 0000_5000H Next descriptor start address — Transfer mode Block transfer Next0 Source Destination Start address 7777_0000H AAAA_0000H Address direction...
Page 338: Next Register Set Continuous Execution Setting
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Start (setting example 4) ⋅ Round robin DCTRL ← 00000001H NXLA_0 ← 00001000 Start link address: 00001000H CHCFG_0 ← 80000000H Set the link mode CHCTRL_0 ← 00000008H ⋅ Clear the status Set 1 in the EN CHCTRL_0 ←...
Page 339 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Start Set DCTRL Set CHITVL Set CHEXT $CR=0 Set CHCFG_n (other settings are optional) REN = 1, RSW = 1, RSEL = $CR, DEM = 0 Set register 0 (N0SA, N0DA, N0TB) Set register 1 (N1SA, N1DA, N1TB) $CR (current register): This variable is for RSEL control.
Page 340: Note
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller Note 9.9.1 Divided Output of DACK0 and TEND0 When transferring 4 bytes or more to an 8-bit or 16-bit external device or transferring 2 bytes or more to an 8-bit external device, each DMA transfer unit is divided into multiple bus cycles.
Page 341: Tend0 Not Output
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 9. Direct Memory Access Controller 9.9.2 TEND0 Not Output Note that TEND0 may not be output depending on the combination of the bits DDS[3:0], SDS[3:0] and REQD in the CHCFG_0 register. Table 9.30 shows when TEND0 is not output and Figure 9.39 shows an operation example. Table 9.30 Bit Combination when TEND0 Is Not Output CHCFG_0 Register...
Page 342: Multi-Function Timer Pulse Unit 2
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Multi-Function Timer Pulse Unit 2 This LSI has an on-chip multi-function timer pulse unit 2 that comprises five 16-bit timer channels. 10.1 Features • Maximum 16 pulse input/output lines •...
Page 343 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.1 Functions of Multi-Function Timer Pulse Unit 2 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Count clock P0φ/1 P0φ/1 P0φ/1 P0φ/1 P0φ/1 P0φ/4 P0φ/4 P0φ/4 P0φ/4...
Page 344 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Interrupt sources 7 sources 4 sources 4 sources 5 sources 5 sources • Compare match • Compare match •...
Page 345 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Figure 10.1 shows a block diagram. Interrupt request signals Channel 3: TGIA_3 Input/output pins TGIB_3 Channel 3: TIOC3A TGIC_3 TIOC3B TGID_3 TIOC3C TCIV_3 TIOC3D Channel 4: TGIA_4 Channel 4: TIOC4A TGIB_4 TIOC4B TGIC_4...
Page 346: Input/Output Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.2 Input/Output Pins Table 10.2 shows the pin configuration Table 10.2 Pin Configuration Channel Pin Name Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input)
Page 347: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3 Register Descriptions Table 10.3 shows the register configuration. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 10.3 Register Configuration Access...
Page 348 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Access Channel Register Name Abbreviation Initial value Address Size Timer general register C_3 TGRC_3 H'FFFF H'FCFF0224 Timer general register D_3 TGRD_3 H'FFFF H'FCFF0226 Timer buffer operation transfer mode register_3 TBTM_3 H'00 H'FCFF0238...
Page 349: Timer Control Register (Tcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. This module has a total of five TCR registers, one each for channels 0 to 4. TCR register settings should be conducted only when TCNT operation is stopped.
Page 350 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.5 CCLR0 to CCLR2 (Channels 1 and 2) Bit 7 Bit 6 Bit 5 Channel Reserved* CCLR1 CCLR0 Description 1, 2 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*...
Page 351 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.9 TPSC0 to TPSC2 (Channels 3 and 4) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description 3, 4 Internal clock: counts on P0φ/1 Internal clock: counts on P0φ/4 Internal clock: counts on P0φ/16 Internal clock: counts on P0φ/64 Internal clock: counts on P0φ/256...
Page 352: Timer Mode Register (Tmdr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. This module has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped.
Page 353 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.10 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 Bit 2 Bit 1 Bit 0 Description Normal operation Setting prohibited PWM mode 1 PWM mode 2* Phase counting mode 1* Phase counting mode 2* Phase counting mode 3*...
Page 354: Timer I/O Control Register (Tior)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. This module has a total of eight TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2. TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode.
Page 355 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 • TIORL_0, TIORL_3, TIORL_4 Bit: IOD[3:0] IOC[3:0] Initial value: R/W: Initial Bit Name Value Description 7 to 4 IOD[3:0] 0000 I/O Control D0 to D3 Specify the function of TGRD. See the following tables.
Page 356 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.11 TIORH_0 (Channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 TGRB_0 Function TIOC0B Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 357 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.12 TIORL_0 (Channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 TGRD_0 Function TIOC0D Pin Function Output compare register* Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 358 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.13 TIOR_1 (Channel 1) Description Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 TGRB_1 Function TIOC1B Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 359 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.14 TIOR_2 (Channel 2) Description Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 TGRB_2 Function TIOC2B Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 360 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.15 TIORH_3 (Channel 3) Description Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 TGRB_3 Function TIOC3B Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 361 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.16 TIORL_3 (Channel 3) Description Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 TGRD_3 Function TIOC3D Pin Function Output compare register* Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 362 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.17 TIORH_4 (Channel 4) Description Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 TGRB_4 Function TIOC4B Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 363 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.18 TIORL_4 (Channel 4) Description Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 TGRD_4 Function TIOC4D Pin Function Output compare register* Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 364 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.19 TIORH_0 (Channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 TGRA_0 Function TIOC0A Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 365 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.20 TIORL_0 (Channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 TGRC_0 Function TIOC0C Pin Function Output compare register* Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 366 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.21 TIOR_1 (Channel 1) Description Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 TGRA_1 Function TIOC1A Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 367 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.22 TIOR_2 (Channel 2) Description Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 TGRA_2 Function TIOC2A Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 368 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.23 TIORH_3 (Channel 3) Description Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 TGRA_3 Function TIOC3A Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 369 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.24 TIORL_3 (Channel 3) Description Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 TGRC_3 Function TIOC3C Pin Function Output compare register* Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 370 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.25 TIORH_4 (Channel 4) Description Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 TGRA_4 Function TIOC4A Pin Function Output compare register Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 371 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.26 TIORL_4 (Channel 4) Description Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 TGRC_4 Function TIOC4C Pin Function Output compare register* Output retained* Initial output is 0 0 output at compare match Initial output is 0...
Page 372: Timer Interrupt Enable Register (Tier)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. This module has six TIER registers, two for channel 0 and one each for channels 1 to 4. •...
Page 373 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Initial Bit Name Value Description TGIEA TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled •...
Page 374: Timer Status Register (Tsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.5 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. This module has six TSR registers, two for channel 0 and one each for channels 1 to 4. •...
Page 375 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Initial Bit Name Value Description TGFC R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved.
Page 376 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 • TSR2_0 Bit: TGFF TGFE Initial value: R/W: R/(W)* R/(W)* Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Initial Bit Name Value...
Page 377: Timer Buffer Operation Transfer Mode Register (Tbtm)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.6 Timer Buffer Operation Transfer Mode Register (TBTM) The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. This module has three TBTM registers, one each for channels 0, 3, and 4.
Page 378: Timer Input Capture Control Register (Ticcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.7 Timer Input Capture Control Register (TICCR) TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. This module has one TICCR in channel 1. Bit: I2BE I2AE...
Page 379: Timer A/D Converter Start Request Control Register (Tadcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.8 Timer A/D Converter Start Request Control Register (TADCR) TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. This module has one TADCR in channel 4. Bit: BF[1:0] UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE...
Page 380 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Initial Bit Name Value Description ITB3AE TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping ITB4VE TCIV_4 Interrupt Skipping Link Enable...
Page 381: Timer A/D Converter Start Request Cycle Set Registers (Tadcora_4 And Tadcorb_4)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.9 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF.
Page 382: Timer General Register (Tgr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.12 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers. This module has eighteen TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers.
Page 383: Timer Start Register (Tstr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.13 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit: CST4 CST3...
Page 384: Timer Synchronous Register (Tsyr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.14 Timer Synchronous Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: SYNC4 SYNC3 SYNC2 SYNC1 SYNC0...
Page 385: Timer Read/Write Enable Register (Trwer)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.15 Timer Read/Write Enable Register (TRWER) TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and 4. Bit: Initial value: R/W:...
Page 386: Timer Output Master Enable Register (Toer)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.16 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4.
Page 387: Timer Output Control Register 1 (Tocr1)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.17 Timer Output Control Register 1 (TOCR1) TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: PSYE TOCL...
Page 388 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.28 Output Level Select Function Bit 1 Function Compare Match Output OLSN Initial Output Active Level Up Count Down Count High level Low level High level Low level Low level High level Low level...
Page 389: Timer Output Control Register 2 (Tocr2)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.18 Timer Output Control Register 2 (TOCR2) TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P...
Page 390 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.30 Setting of Bits BF1 and BF0 Bit 7 Bit 6 Description Complementary PWM Mode Reset-Synchronized PWM Mode Does not transfer data from the buffer register Does not transfer data from the buffer register (TOLBR) to TOCR2.
Page 391 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.35 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up Count Down Count High level Low level High level Low level Low level High level...
Page 392: Timer Output Level Buffer Register (Tolbr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.19 Timer Output Level Buffer Register (TOLBR) TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Initial value:...
Page 393: Timer Gate Control Register (Tgcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.20 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/reset-synchronized PWM mode.
Page 394: Timer Subcounter (Tcnts)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.37 Output level Select Function Function Bit 2 Bit 1 Bit 0 TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D U Phase V Phase W Phase U Phase V Phase W Phase 10.3.21 Timer Subcounter (TCNTS)
Page 395: Timer Cycle Data Register (Tcdr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.23 Timer Cycle Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier cycle value (however, the value must also be at least twice the setting of TDDR plus 3) as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment).
Page 396: Timer Interrupt Skipping Set Register (Titcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.25 Timer Interrupt Skipping Set Register (TITCR) TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. This module has one TITCR. Bit: T3AEN 3ACOR[2:0]...
Page 397 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.38 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 Bit 5 Bit 4 3ACOR2 3ACOR1 3ACOR0 Description Does not skip TGIA_3 interrupts. Sets the TGIA_3 interrupt skipping count to 1. Sets the TGIA_3 interrupt skipping count to 2.
Page 398: Timer Interrupt Skipping Counter (Titcnt)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.26 Timer Interrupt Skipping Counter (TITCNT) TITCNT is an 8-bit readable counter. This module has one TITCNT. TITCNT retains its value even after stopping the count operation of TCNT_3 and TCNT_4. Bit: 3ACNT[2:0] 4VCNT[2:0]...
Page 399: Timer Buffer Transfer Set Register (Tbter)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.27 Timer Buffer Transfer Set Register (TBTER) TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation.
Page 400: Timer Dead Time Enable Register (Tder)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.28 Timer Dead Time Enable Register (TDER) TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. This module has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: TDER Initial value:...
Page 401: Timer Waveform Control Register (Twcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.3.29 Timer Waveform Control Register (TWCR) TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match.
Page 402: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4 Operation 10.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register.
Page 403 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (b) Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the TCNT counters of this module are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 404 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (2) Waveform Output by Compare Match This module can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match Figure 10.7 shows an example of the setting procedure for waveform output by compare match.
Page 405 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Figure 10.9 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF...
Page 406 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source.
Page 407 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (b) Example of Input Capture Operation Figure 10.11 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 408: Synchronous Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing).
Page 409 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (2) Example of Synchronous Operation Figure 10.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 410: Buffer Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 411 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (1) Example of Buffer Operation Setting Procedure Figure 10.16 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or Buffer operation output compare register by means of TIOR.
Page 412 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (b) When TGR is an input capture register Figure 10.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 413 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4).
Page 414: Cascaded Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Page 415 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (1) Example of Cascaded Operation Setting Procedure Figure 10.20 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 Cascaded operation TCR to B'111 to select TCNT_2 overflow/ underflow counting.
Page 416 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (3) Cascaded Operation Example (b) Figure 10.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing.
Page 417 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (4) Cascaded Operation Example (c) Figure 10.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively.
Page 418 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (5) Cascaded Operation Example (d) Figure 10.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing.
Page 419: Pwm Modes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty.
Page 420 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (1) Example of PWM Mode Setting Procedure Figure 10.25 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR.
Page 421 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Figure 10.27 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform.
Page 422 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Figure 10.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA...
Page 423: Phase Counting Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/ decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/ down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR.
Page 424 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 10.30 shows an example of phase counting mode 1 operation, and Table 10.46 summarizes the TCNT up/down- count conditions.
Page 425 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (b) Phase counting mode 2 Figure 10.31 shows an example of phase counting mode 2 operation, and Table 10.47 summarizes the TCNT up/down- count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2)
Page 426 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Phase counting mode 3 Figure 10.32 shows an example of phase counting mode 3 operation, and Table 10.48 summarizes the TCNT up/down- count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value...
Page 427 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (d) Phase counting mode 4 Figure 10.33 shows an example of phase counting mode 4 operation, and Table 10.49 summarizes the TCNT up/down- count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2)
Page 428 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (3) Phase Counting Mode Application Example Figure 10.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed.
Page 429: Reset-Synchronized Pwm Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT_3 functions as an upcounter.
Page 430 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (1) Procedure for Selecting the Reset-Synchronized PWM Mode Figure 10.35 shows an example of procedure for selecting the reset synchronized PWM mode. [1] Clear the CST3 and CST4 bits in the TSTR Reset-synchronized to 0 to halt the counting of TCNT.
Page 431 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (2) Reset-Synchronized PWM Mode Operation Figure 10.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins incrementing from H'0000.
Page 432: Complementary Pwm Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without non-overlapping interval are also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period.
Page 433 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Table 10.53 Register Settings for Complementary PWM Mode Channel Counter/Register Description Read/Write from CPU TCNT_3 Start of up-count from value set in dead time register Maskable by TRWER setting* TGRA_3 Set TCNT_3 upper limit value (1/2 carrier cycle + dead Maskable by TRWER setting*...
Page 434 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 TGRC_3 TCBR TDDR TGRA_3 TCDR PWM cycle output Comparator Match PWM output 1 signal PWM output 2 TCNT_3 TCNTS TCNT_4 PWM output 3 PWM output 4 PWM output 5 Comparator Match PWM output 6...
Page 435 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (1) Example of Complementary PWM Mode Setting Procedure An example of the complementary PWM mode setting procedure is shown in Figure 10.38. [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation.
Page 436 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (2) Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 10.39 illustrates counter operation in complementary PWM mode, and Figure 10.40 shows an example of complementary PWM mode operation. (a) Counter Operation In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform up/down-count operations.
Page 437 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (b) Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 10.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4.
Page 438 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Transfer from temporary Transfer from temporary register to compare register register to compare register TGRA_3 TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register H'6400 H'0080 TGRC_4 Temporary register H'6400 H'0080...
Page 439 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set.
Page 440 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (d) PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6-phase output.
Page 441 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Transfer from temporary register Transfer from temporary register to compare register to compare register TGRA_3=TCDR+1 TCNTS TCDR TCNT_3 TCNT_4 TGRA_4 TGRC_4 TDDR=1 H'0000 Buffer register TGRC_4 Data1 Data2 Data1 Data2 Temporary register TEMP2...
Page 442 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (g) PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 setting = TCDR setting + TDDR setting TCDR setting >...
Page 443 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (h) Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation.
Page 444 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Figure 10.43 Example of Data Update in Complementary PWM Mode R01UH0437EJ0600 Rev.6.00 10-103 Jan 29, 2021...
Page 445 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR).
Page 446 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TCNT_3 TCNT_4 TDDR TGRA_4...
Page 447 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and compare register.
Page 448 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 T2 period T1 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 10.46 Example of Complementary PWM Mode Waveform Output (1) T2 period T1 period T1 period TGRA_3 TCDR...
Page 449 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 10.48 Example of Complementary PWM Mode Waveform Output (3) T1 period T2 period T1 period TGRA_3 TCDR...
Page 450 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 10.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period T2 period T1 period TGRA_3...
Page 451 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 c b' d a' Positive phase Negative phase Figure 10.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period T2 period T1 period...
Page 452 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figure 10.49 to Figure 10.53 show output examples. 100% duty output is performed when the compare register value is set to H'0000.
Page 453 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (m) Counter Clearing by Another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel.
Page 454 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing.
Page 455 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 • Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in Figure 10.57.
Page 456 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 10.56;...
Page 457 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Initial value output is suppressed. Negative phase Output waveform is active-low. Figure 10.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 10.56;...
Page 458 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (o) Counter Clearing by TGRA_3 Compare Match In complementary PWM mode, by setting the CCE bit in the timer waveform control register (TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare match. Figure 10.62 illustrates an operation example.
Page 459 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (p) Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR).
Page 460 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 10.64 Example of Output Phase Switching by External Input (2) TGCR...
Page 461 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 10.66 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) (q) A/D Converter Start Request Setting...
Page 462 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (3) Interrupt Skipping in Complementary PWM Mode Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up to seven times by making settings in the timer interrupt skipping set register (TITCR).
Page 463 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 TCNT_3 TCNT_4 Period during which Period during which Period during which Period during which changing skipping count changing skipping count changing skipping count changing skipping count can be performed can be performed can be performed can be performed...
Page 464 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE1 and BTE0 bits in the timer buffer transfer set register (TBTER).
Page 465 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (1)When rewriting the buffer register within 1 carrier cycle from TGIA_3 interrupt TGIA_3 interrupt generation TGIA_3 interrupt generation TCNT_3 TCNT_4 Buffer register rewrite timing Buffer register rewrite timing Buffer transfer- enabled period TITCR[6:4]...
Page 466 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Skipping counter 3ACNT Skipping counter 4VCNT Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) Note: * The MD bits 3 to 0 = 1111 in TMDR_3, buffer transfer at the crest and the trough is selected.
Page 467: A/D Converter Start Request Delaying Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4).
Page 468 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 • Basic Operation Example of A/D Converter Start Request Delaying Function Figure 10.74 shows a basic example of A/D converter request signal (TRG4AN) operation when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request signal is output during TCNT_4 down-counting.
Page 469 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping...
Page 470: Tcnt Capture At Crest And/Or Trough In Complementary Pwm Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation.
Page 471: Interrupt Sources
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.5 Interrupt Sources 10.5.1 Interrupt Sources and Priorities This module has three kinds of interrupt sources; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
Page 472: Activation Of Direct Memory Access Controller
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel.
Page 473 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (2) A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0 The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0.
Page 474: Operation Timing
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.6 Operation Timing 10.6.1 Input/Output Timing (1) TCNT Count Timing Figure 10.78 shows TCNT count timing in internal clock operation, and Figure 10.79 shows TCNT count timing in external clock operation (normal mode), and Figure 10.80 shows TCNT count timing in external clock operation (phase counting mode).
Page 475 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
Page 476 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (3) Input Capture Signal Timing Figure 10.83 shows input capture signal timing. P0φ Input capture input Input capture signal N + 1 N + 2 TCNT N + 2 Figure 10.83 Input Capture Input Signal Timing (4) Timing for Counter Clearing by Compare Match/Input Capture...
Page 477 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (5) Buffer Operation Timing Figure 10.86 to Figure 10.88 show the timing in buffer operation. P0φ TCNT n + 1 Compare match buffer signal TGRA, TGRB TGRC, TGRD Figure 10.86 Buffer Operation Timing (Compare Match) P0φ...
Page 478 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (6) Buffer Transfer Timing (Complementary PWM Mode) Figure 10.89 to Figure 10.91 show the buffer transfer timing in complementary PWM mode. P0φ TCNTS H'0000 TGRD_4 write signal Temporary register transfer signal Buffer register...
Page 479: Interrupt Signal Timing
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.6.2 Interrupt Signal Timing (1) TGF Flag Setting Timing in Case of Compare Match Figure 10.92 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
Page 480 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (3) TCFV Flag/TCFU Flag Setting Timing Figure 10.94 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 10.95 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing.
Page 481 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the direct memory access controller is activated, the flag is cleared automatically.
Page 482: Usage Notes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7 Usage Notes 10.7.1 Module Standby Mode Setting Operation of this module can be disabled or enabled using the standby control register. The initial setting is for the operation to be halted.
Page 483: Caution On Period Setting
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: P0φ...
Page 484: Contention Between Tcnt Write And Increment Operations
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Page 485: Contention Between Buffer Register Write And Compare Match
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data after write.
Page 486: Contention Between Buffer Register Write And Tcnt Clear
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.8 Contention between Buffer Register Write and TCNT Clear When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write.
Page 487: Contention Between Tgr Write And Input Capture
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.10 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed.
Page 488: Tcnt_2 Write And Overflow/Underflow Contention In Cascade Connection
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled.
Page 489: Counter Value During Complementary Pwm Mode Stop
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.13 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state.
Page 490: Reset Sync Pwm Mode Buffer Operation And Compare Match Flag
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1.
Page 491: Overflow Flags In Reset Synchronous Pwm Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.16 Overflow Flags in Reset Synchronous PWM Mode When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting.
Page 492: Contention Between Tcnt Write And Overflow/Underflow
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.18 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Page 493: Simultaneous Capture Of Tcnt_1 And Tcnt_2 In Cascade Connection
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B.
Page 494 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 Synchronous clearing (10) (11) (10) (11) TGRA_3 TCNT_3 Tb interval Tb interval TCNT_4 TDDR PWM output (positive phase) PWM output (negative phase) Active-level output occurs at synchronous clearing Nonexistent even though no active-level output interval has been set.
Page 495: Output Pin Initialization For Multi-Function Timer Pulse Unit 2
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.8 Output Pin Initialization for Multi-Function Timer Pulse Unit 2 10.8.1 Operating Modes This module has the following six operating modes. Waveform output is possible in all of these modes. •...
Page 496: Operation In Case Of Re-Setting Due To Error During Operation, Etc
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc. If an error occurs during operation of this module, the module output should be cut by the system. Cutoff is performed by switching the pin output to port output with the general I/O port and outputting the inverse of the active level.
Page 497: Overview Of Initialization Procedures And Mode Transitions In Case Of Error During Operation, Etc
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. • When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting.
Page 498 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode Figure 10.115 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting.
Page 499 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 10.116 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
Page 500 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 10.117 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
Page 501 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 10.118 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
Page 502 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.119 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
Page 503 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 10.120 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 504 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode Figure 10.121 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
Page 505 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1 Figure 10.122 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
Page 506 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (9) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2 Figure 10.123 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
Page 507 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 10.124 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
Page 508 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.125 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
Page 509 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 10.126 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 510 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 10.127 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
Page 511 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 10.128 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
Page 512 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 10.129 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
Page 513 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 10.130 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting.
Page 514 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 10.131 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
Page 515 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 10.132 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
Page 516 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 10.133 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
Page 517 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 10.134 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting.
Page 518 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 10.135 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
Page 519 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 10.136 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 520 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.137 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped).
Page 521 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.138 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings).
Page 522 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 10.139 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode.
Page 523 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (26) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 10.140 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting.
Page 524 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (27) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 10.141 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 525 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (28) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.142 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting.
Page 526 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 10. Multi-Function Timer Pulse Unit 2 (29) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 10.143 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 527: Os Timer
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer OS Timer 11.1 Functional Overview The OS timer has the following features. • Two operating modes – Interval timer mode – Free-running comparison mode • Choice between startup of DMA by compare match and generation of interrupt 11.1.1 Features of OSTM Channels...
Page 528: Registers
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer 11.2 Registers The OS timer is controlled and operated by the following registers. 11.2.1 Registers Overview The list of OSTMn (n = 0, 1) registers and the memory addresses are as follows. For the base addresses, see the Table 11.2.
Page 529: Details Of Ostm Registers
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer 11.2.2 Details of OSTM Registers — 11.2.2.1 OSTMnCMP OSTM Compare Register Depending on the mode of operation, this register holds the start value for the down-counter or the value for comparison with that of the counter. Access: This register is readable/writable in 32-bit units.
Page 530 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer — 11.2.2.2 OSTMnCNT OSTM Counter Register This register indicates the counter value of the timer. Access: This register is readable in 32-bit units. Address: OSTMn_base> + 4 Initial value: The initial value depends on the operating mode of the OS timer. Refer to Table 11.6, Correspondence between Operating Mode, Counting Direction and Initial Value.
Page 531 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer — 11.2.2.3 OSTMnTE OSTM Count Enable Status Register This register indicates whether the counter is enabled or disabled. Access: This register is readable in 8-bit units. Address: <OSTMn_base>+ 10 Initial value: OSTMnTE Table 11.7 OSTMnTE register contents...
Page 532 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer — 11.2.2.5 OSTMnTT OSTM Count Stop Trigger Register This register stops the counter. Access: This register is writable in 8-bit units. It is always read as 00 Address: <OSTMn_base>+ 18 Initial value: OSTMnTT Table 11.9 OSTMnTT register contents...
Page 533: Functional Description
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer 11.3 Functional Description Each OS timer is a 32-bit timer/counter. The settings for operating mode specify the direction of counting (up or down) and the generation of interrupt requests. 11.3.1 Block Diagram The following block diagram shows the main components of OSTM.
Page 534: Count Clock
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer 11.3.2 Count Clock The count clock of OSTMn is P0φ. 11.3.3 Generation of Interrupt Request An OSTMnTINT interrupt request is generated whenever the counter reaches 0000 0000 (in interval timer mode) or matches the comparison value (in free-running comparison mode). An interrupt request can also be generated on starting and restarting of the counter.
Page 535: Starting And Stopping The Timer
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer 11.3.4 Starting and Stopping the Timer The OS timer is started and stopped as follows. Starting the timer The timer is started in either of the following way: • setting the OSTMnTS.OSTMnTSF bit to 1 Status bit OSTMnTE.OSTMnTE is set to 1.
Page 536 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer The following figure shows the basic operation of OSTM when counter-start interrupts is enabled in interval timer mode. OSTMnTS OSTMnTT Counter operating Counter operating OSTMnTE OSTMnCMP FFFF FFFF OSTMnCNT 0000 0000 A + 1 A + 1 B + 1...
Page 537 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer The following figure shows the forced restart of the OS Timer in interval timer mode, with counter- start interrupts enabled (OSTMnCTL.OSTMnMD0 = 1). OSTMnTS OSTMnTT Counter operating OSTMnTE OSTMnCMP FFFF FFFF OSTMnCNT 0000 0000 OSTMTINT...
Page 538 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer 11.3.5.2 Operation when OSTMnCMP = 0000 0000 When OSTMnCMP = 0000 0000 , OSTM behaves as follows. • When the counter is enabled, the OSTMTINT interrupt request is always set to 1. The following figure shows operations of OSTM when OSTMnCMP = 0000 0000 , and counter-start interrupts are enabled.
Page 539: Free-Running Comparison Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer 11.3.6 Free-Running Comparison Mode 11.3.6.1 Basic Operation in Free-Running Comparison Mode In free-running comparison mode, the counter counts up from 0000 0000 to FFFF FFFF . An OSTMnTINT interrupt request is output when the current value of the counter matches the value of the OSTMnCMP register.
Page 540 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer OSTMTINT period The OSTMTINT generation period is different at the start of counting and depends on the old and new compare values if OSTMnCMP is rewritten during operation. Table 11.11 OSTMTINT Generation Timing Label in Old Value for New Value for...
Page 541 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 11. OS Timer Every (FFFF FFFF + 1) clock cycles the OSTMTINT interrupt request is asserted. When interrupts on starting of the counter are disabled, no interrupt is generated when counting starts. R01UH0437EJ0600 Rev.6.00 11-15 Jan 29, 2021...
Page 542: Watchdog Timer
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer Watchdog Timer This LSI includes the watchdog timer, which externally outputs an overflow signal (WDTOVF) on overflow of the counter when the value of the counter has not been updated because of a system malfunction. This module can simultaneously generate an internal reset signal for the entire LSI.
Page 543: Input/Output Pin
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer 12.2 Input/Output Pin Table 12.1 shows the pin configuration. Table 12.1 Pin Configuration Pin Name Symbol Function Watchdog timer overflow WDTOVF Output Outputs the counter overflow signal in watchdog timer mode 12.3 Register Descriptions Table 12.2 shows the register configuration.
Page 544: Watchdog Timer Counter (Wtcnt)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer 12.3.1 Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in watchdog timer mode and an interrupt in interval timer mode.
Page 545 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer Initial Bit Name Value Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using this module in software standby mode or when changing the clock frequency. 0: Timer disabled Count-up stops and WTCNT value is retained 1: Timer enabled...
Page 546: Watchdog Reset Control/Status Register (Wrcsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer 12.3.3 Watchdog Reset Control/Status Register (WRCSR) WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal generated by watchdog timer counter (WTCNT) overflow. Note: The method for writing to WRCSR differs from that for other registers to prevent erroneous writes. See section 12.3.4, Notes on Register Access for details.
Page 547: Notes On Register Access
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer 12.3.4 Notes on Register Access The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and watchdog reset control/ status register (WRCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below.
Page 548 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer (3) Reading from WTCNT, WTCSR, and WRCSR WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is allocated to address H'FCFE0000, WTCNT to address H'FCFE0002, and WRCSR to address H'FCFE0004. Eight-bit transfer instructions must be used for reading from these registers.
Page 549: Usage
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer 12.4 Usage 12.4.1 Canceling Software Standby Mode This module can be used to cancel software standby mode with an interrupt such as an NMI interrupt. The procedure is described below. (This module does not operate when resets are used for canceling, so keep the RES pin low until clock oscillation settles.) 1.
Page 550: Using Interval Timer Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer WTCNT value Overflow H'FF H'00 Time H'00 written WOVF = 1 H'00 written WT/IT = 1 in WTCNT in WTCNT TME = 1 WDTOVF and internal reset generated WDTOVF signal 64 × P0φ clock cycles Internal reset signal* 128 ×...
Page 551: Usage Notes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 12. Watchdog Timer 12.5 Usage Notes Pay attention to the following points when using this module in either the interval timer or watchdog timer mode. 12.5.1 Timer Variation After timer operation has started, the period from the power-on reset point to the first count up timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR.
Page 552: Realtime Clock
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock Realtime Clock This LSI has a realtime clock and a 32.768-kHz crystal oscillator. 13.1 Features • Clock and calendar functions (BCD format): Seconds, minutes, hours, day of the week, day, month, and year. •...
Page 553 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock Figure 13.1 shows the block diagram. RTC_X1 32.768 kHz Crystal oscillator RTC_X2 128 Hz Prescaler R64CNT RSECCNT RSECAR RMINAR EXTAL RMINCNT Crystal oscillator RHRCNT RHRAR RCR5 XTAL RFRH RDAYAR RDAYCNT RFRL Operation RWKAR RWKCNT...
Page 554: Input/Output Pin
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.2 Input/Output Pin Table 13.1 shows the pin configuration. Table 13.1 Pin Configuration Pin Name Symbol Description Realtime clock crystal RTC_X1 Input Connects a 32.768-kHz crystal resonator for this module. resonator pin/external clock External clock can be input to the RTC_X1 pin.
Page 555: 64-Hz Counter (R64Cnt)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.1 64-Hz Counter (R64CNT) R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz. Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the control register 1 (RCR1) to 1, which indicates that the carrying and reading the 64-Hz counter are performed at the same time.
Page 556: Second Counter (Rseccnt)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.2 Second Counter (RSECCNT) RSECCNT is the counter used for setting/counting the BCD-coded second value. The count operation is performed by a carry for each second of the 64-Hz counter. The assignable range is from 00 through 59 (practically in BCD); otherwise an operation error will occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2.
Page 557: Hour Counter (Rhrcnt)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.4 Hour Counter (RHRCNT) RHRCNT is the counter used for setting/counting the BCD-coded hour value. The count operation is performed by a carry for each 1 hour of the minute counter. The assignable range is from 00 through 23 (practically in BCD);...
Page 558: Day Counter (Rdaycnt)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.6 Day Counter (RDAYCNT) RDAYCNT is the counter used for setting/counting the BCD-coded day value. The count operation is performed by a carry for each day of the hour counter. The assignable range is from 01 through 31 (practically in BCD); otherwise an operation error will occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2.
Page 559: Year Counter (Ryrcnt)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.8 Year Counter (RYRCNT) RYRCNT is the counter used for setting/counting the BCD-coded year value. The count operation is performed by a carry for each year of the month counter. The assignable range is from 0000 through 9999 (practically in BCD); otherwise an operation error will occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2.
Page 560: Minute Alarm Register (Rminar)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.10 Minute Alarm Register (RMINAR) RMINAR is an alarm register corresponding to the BCD-coded minute counter RMINCNT. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/ RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1.
Page 561: Day Of Week Alarm Register (Rwkar)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.12 Day of Week Alarm Register (RWKAR) RWKAR is an alarm register corresponding to the BCD-coded day of week counter RWKCNT. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/ RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1.
Page 562: Month Alarm Register (Rmonar)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.14 Month Alarm Register (RMONAR) RMONAR is an alarm register corresponding to the BCD-coded month counter RMONCNT. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/ RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1.
Page 563: Control Register 1 (Rcr1)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.16 Control Register 1 (RCR1) RCR1 is a register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. The CF flag remains undefined until the divider circuit is reset (the RESET and ADJ bits in RCR2 are set to 1). When using the CF flag, make sure to reset the divider circuit beforehand.
Page 564: Control Register 2 (Rcr2)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.17 Control Register 2 (RCR2) RCR2 is a register for periodic interrupt control, 30-second adjustment, divider circuit RESET, and count control. RCR2 is initialized by a power-on reset or in deep standby mode. The RTCEN bit is only initialized by a power-on reset using the RES pin.
Page 565: Control Register 3 (Rcr3)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.18 Control Register 3 (RCR3) When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among RSECAR/RMINAR/ RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1.
Page 566: Frequency Register H/L (Rfrh/L)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.3.20 Frequency Register H/L (RFRH/L) RFRH/L is a 16-bit readable/writable register. The "frequency comparison value" is set in RFC[18:0] so that a 128-Hz clock is generated when the realtime clock operates at the EXTAL clock frequency. Change the "frequency comparison value"...
Page 567: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.4 Operation A usage example of this module is shown below. 13.4.1 Initial Settings of Registers after Power-On and Oscillation Stabilization Time All the registers should be initialized after the power is turned on. When the RTC_X1 crystal oscillator is used, oscillation stabilization time is necessary after changing the RTCEN bit in RCR2 from 0 to 1.
Page 568: Reading Time
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.4.3 Reading Time Figure 13.3 shows how to read the time. Write 0 to CIE in RCR1 Disable the carry interrupt Write 0 to CF in RCR1 Clear the carry flag (Set AF in RCR1 to 1 so that alarm flag is not cleared.) Read all the counter registers...
Page 569: Alarm Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.4.4 Alarm Function Figure 13.4 shows how to use the alarm function. Clock running Write 0 to AIE in RCR1 Disable alarm interrupt to prevent erroneous interrupt Set alarm time Always reset, since the flag may have been Clear alarm flag set while the alarm time was being set.
Page 570: Usage Notes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 13. Realtime Clock 13.5 Usage Notes 13.5.1 Register Writing during Count Operation The following registers cannot be written to during count operation (while the START bit = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCONT Count operation must be stopped before writing to any of the above registers.
Page 571: Serial Communication Interface With Fifo
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Serial Communication Interface with FIFO This LSI has a five-channel serial communication interface with FIFO that supports both asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication.
Page 572 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Figure 14.1 shows a block diagram. However, certain channels do not have the CTS and RTS pins. Module data bus Peripheral SCFRDR (16 stages) SCFTDR (16 stages) SCSMR SCBRR SCLSR SCEMR...
Page 573: Input/Output Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.2 Input/Output Pins Table 14.1 shows the pin configuration. Table 14.1 Pin Configuration Channel Pin Name Symbol Function 0 to 4 Serial clock pins SCK0 to SCK4 Clock I/O Receive data pins RxD0 to RxD4 Input...
Page 574: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3 Register Descriptions This module has the following registers. Table 14.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Serial mode register_0 SCSMR_0 H'0000 H'E8007000 Bit rate register_0 SCBRR_0 H'FF...
Page 575: Receive Shift Register (Scrsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Access Channel Register Name Abbreviation Initial Value Address Size Serial mode register_4 SCSMR_4 H'0000 H’E8009000 Bit rate register_4 SCBRR_4 H'FF H’E8009004 Serial control register_4 SCSCR_4 H'0000 H’E8009008 Transmit FIFO data register_4 SCFTDR_4 Undefined H’E800900C...
Page 576: Transmit Shift Register (Sctsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.3 Transmit Shift Register (SCTSR) SCTSR transmits serial data. Transmit data is loaded from the transmit FIFO data register (SCFTDR) into SCTSR, then the data is transmitted serially from the TxD pin, LSB (bit 0) first. After one data byte has been transmitted, the next transmit data is automatically loaded from SCFTDR into SCTSR and transmission is started again.
Page 577: Serial Mode Register (Scsmr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.5 Serial Mode Register (SCSMR) SCSMR specifies the serial communication format and selects the clock source for the baud rate generator. The CPU can always read from and write to SCSMR. Bit: STOP CKS[1:0]...
Page 578 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Initial Bit Name Value Description STOP Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added.
Page 579: Serial Control Register (Scscr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.6 Serial Control Register (SCSCR) SCSCR enables/disables the transmitter/receiver operation and interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: REIE CKE[1:0]...
Page 580 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Initial Bit Name Value Description REIE Receive Error Interrupt Enable Enables or disables the receive-error (ERI) interrupts and break (BRI) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests are disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests are enabled* Note: * ERI or BRI interrupt requests can be cleared by reading the ER, BRK or...
Page 581: Serial Status Register (Scfsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.7 Serial Status Register (SCFSR) SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive FIFO data register, and the lower 8 bits indicate the status flag indicating operating state. The CPU can always read from and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR).
Page 582 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Initial Bit Name Value Description TEND R/(W)* Transmit End Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition] •...
Page 583 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Initial Bit Name Value Description Framing Error Indication Indicates a framing error in the data read from the receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions] •...
Page 584 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Initial Bit Name Value Description R/(W)* Receive Data Ready Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode.
Page 585: Bit Rate Register (Scbrr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.8 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that is used with the CKS[1:0] bits in the serial mode register (SCSMR) and the BGDM and ABCS bits in the serial extension mode register (SCEMR) to determine the serial transmit/receive bit rate. The CPU can always read from and write to SCBRR.
Page 586 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO • Clock synchronous mode: P1φ × 10 − 1 8 × 2 × B 2n-1 Bit rate (bits/s) SCBRR setting for baud rate generator (0 ≤ N ≤ 255) (The setting must satisfy the electrical characteristics.) P1φ: Operating frequency for peripheral modules (MHz)
Page 587 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Table 14.4 lists the sample SCBRR settings in asynchronous mode in which a base clock frequency is 16 times the bit rate (the ABCS bit in SCEMR is 0) and the baud rate generator operates in normal mode (the BGDM bit in SCEMR is 0), and Table 14.5 lists the sample SCBRR settings in clock synchronous mode.
Page 588 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Table 14.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Table 14.7 lists the maximum bit rates in asynchronous mode when the external clock input is used. Table 14.8 lists the maximum = 12t bit rates in clock synchronous mode when the external clock input is used (when t Scyc...
Page 589: Fifo Control Register (Scfcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.9 FIFO Control Register (SCFCR) SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. Bit: RSTRG[2:0] RTRG[1:0]...
Page 590 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Initial Bit Name Value Description TFRST Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the register to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.
Page 591: Fifo Data Count Set Register (Scfdr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.10 FIFO Data Count Set Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits.
Page 592: Serial Port Register (Scsptr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.11 Serial Port Register (SCSPTR) SCSPTR controls input/output and data of pins multiplexed to the functions of this module. Bits 7 and 6 can control input/output data of RTS pin. Bits 5 and 4 can control input/output data of CTS pin. Bits 3 and 2 can control input/output data of SCK pin.
Page 593 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Initial Bit Name Value Description SPB2IO Serial Port Break Input/Output Specifies input or output for the serial port TxD pin. When the TxD pin is actually used as a port outputting the SPB2DT bit value, the TE bit in SCSCR should be cleared to 0.
Page 594: Line Status Register (Sclsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.12 Line Status Register (SCLSR) The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1).
Page 595: Serial Extension Mode Register (Scemr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.3.13 Serial Extension Mode Register (SCEMR) The CPU can always read from or write to SCEMR. Setting the BGDM bit in this register to 1 allows the baud rate generator in this module to operate in double-speed mode when asynchronous mode is selected (by setting the C/A bit in SCSMR to 0) and an internal clock is selected as a clock source and the SCK pin is set as an input pin (by setting the CKE[1:0] bits in SCSCR to 00).
Page 596: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.4 Operation 14.4.1 Overview For serial communication, this module has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. This module has a 16-stage FIFO buffer for both transmission and reception, reducing the overhead of the CPU, and enabling continuous high-speed communication.
Page 597 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO (2) Clock Synchronous Mode • The transmission/reception format has a fixed 8-bit data length. • In receiving, it is possible to detect overrun errors (ORER). • An internal or external clock can be selected as the clock source. —...
Page 598: Operation In Asynchronous Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections in this module are independent, so full duplex communication is possible.
Page 599 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO (1) Transmit/Receive Formats Table 14.11 lists the eight communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 14.11 Serial Communication Formats (Asynchronous Mode) Serial Transmit/Receive Format and Frame Length...
Page 600 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and the CKE[1:0] bits in the serial control register (SCSCR).
Page 601 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Figure 14.3 shows a sample flowchart for initialization. Start of initialization Clear the TE and RE bits in SCSCR to 0 Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0.
Page 602 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO • Transmitting Serial Data (Asynchronous Mode) Figure 14.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling transmission. Start of transmission [1] Status check and transmit data write: Read SCFSR and check that the Read TDFE flag in SCFSR...
Page 603 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO In serial transmission, this module operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the data is transferred from SCFTDR to the transmit shift register (SCTSR).
Page 604 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Figure 14.5 shows an example of the operation for transmission. Start Parity Stop Start Parity Stop Data Data Serial Idle state data (mark state) TDFE TEND TXI interrupt Data written to SCFTDR and TDFE TXI interrupt request...
Page 605 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO • Receiving Serial Data (Asynchronous Mode) Figure 14.7 and Figure 14.8 show sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling reception. [1] Receive error handling and Start of reception break detection:...
Page 606 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Error handling • Whether a framing error or parity error has occurred in the receive data that ORER = 1? is to be read from the receive FIFO data register (SCFRDR) can be ascertained from the FER and PER bits in the serial status register...
Page 607 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO In serial reception, this module operates as described below. 1. The transmission line is monitored, and if a 0 start bit is detected, internal synchronization is performed and reception is started.
Page 608 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Figure 14.9 shows an example of the operation for reception in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Serial Idle state data (mark state) RXI interrupt request Data read and RDF flag One frame...
Page 609: Operation In Clock Synchronous Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.4.3 Operation in Clock Synchronous Mode In clock synchronous mode, data is transmitted and received in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The transmitter and receiver in this module are independent, so full-duplex communication is possible while sharing the same clock.
Page 610 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO (1) Transmit/Receive Formats The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator or an external synchronous clock input from the SCK pin can be selected by setting the C/A bit in SCSMR and the CKE[1:0] bits in SCSCR,.
Page 611 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Figure 14.12 shows a sample flowchart for initialization. Start of initialization Leave the TE and RE bits cleared to 0 until the initialization almost ends. Clear TE and RE bits in SCSCR to 0 Set the data transfer format in SCSMR.
Page 612 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO • Transmitting Serial Data (Clock Synchronous Mode) Figure 14.13 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling transmit operation. Start of transmission [1] Status check and transmit data write: Read SCFSR and check that the...
Page 613 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO In serial transmission, this module operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the data is transferred from SCFTDR to the transmit shift register (SCTSR).
Page 614 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO • Receiving Serial Data (Clock Synchronous Mode) Figure 14.15 and Figure 14.16 show sample flowcharts for receiving serial data. Use the following procedure for serial data reception after enabling receive operation. When switching from asynchronous mode to clock synchronous mode without initialization, make sure that ORER, PER, and FER are cleared to 0.
Page 615 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO In serial reception, this module operates as described below. 1. Reception is started in synchronization with synchronous clock input or output. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After the data reception, whether the receive data can be loaded from SCRSR into SCFRDR or not is checked.
Page 616 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO • Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode) Figure 14.18 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for the simultaneous transmission/reception of serial data, after enabling transmit/ receive operation.
Page 617: Interrupts
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.5 Interrupts This module has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive FIFO data full (RXI), and break (BRI). Table 14.12 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR.
Page 618: Usage Notes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.6 Usage Notes Note the following when using this module. 14.6.1 SCFTDR Writing and TDFE Flag The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG[1:0] in the FIFO control register (SCFCR).
Page 619: Sending A Break Signal
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO 14.6.5 Sending a Break Signal The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, the TxD pin does not work.
Page 620: Selection Of Base Clock In Asynchronous Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 14. Serial Communication Interface with FIFO Equation 2: When D = 0.5 and F = 0: M = (0.5 − 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. 14.6.7 Selection of Base Clock in Asynchronous Mode In this LSI, when asynchronous mode is selected, the base clock frequency within a bit period can be set to the frequency...
Page 621: Serial Communications Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Serial Communications Interface This LSI has two independent serial communications interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communications. Asynchronous serial data communications can be carried out with standard asynchronous communications chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA).
Page 622 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Module data bus SCMR P1φ Baud rate SCI_RXD P1φ /4 generator SEMR P1φ /16 SCI_TXD SNFR P1φ /64 SECR SCI_CTS/ Transmission Parity error occurrence and reception Parity check Clock control External clock SCI_SCK RSR: Receive shift register...
Page 623: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2 Register Descriptions Table 15.3 is a list of registers. Table 15.3 List of Registers Channel Register Name Symbol Value after Reset Address Access size Serial mode register 0 SMR0 H'00 H'E800B000 Bit rate register 0...
Page 624: Receive Shift Register (Rsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RXDn pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 625: Serial Mode Register (Smr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2.5 Serial Mode Register (SMR) Note: • Some bits in SMR have different functions in serial communications interface mode and smart card interface mode. (1) Serial Communications Interface Mode (SMIF in SCMR = 0) STOP CKS[1:0] Value after reset:...
Page 626 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface PM Bit (Parity Mode) Selects the parity mode (even or odd) for transmission and reception. The setting of the PM bit is invalid in multi-processor mode. PE Bit (Parity Enable) When this bit is set to 1, the parity bit is added to transmit data, and the parity bit is checked in reception.
Page 627 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface BCP[1:0] Bits (Base Clock Pulse) These bits select the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set these bits in combination with the BCP2 bit in SCMR. For details, see section 15.6.4, Receive Data Sampling Timing and Reception Margin.
Page 628: Serial Control Register (Scr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2.6 Serial Control Register (SCR) Note: • Some bits in SCR have different functions in serial communications interface mode and smart card interface mode. (1) Serial Communications Interface Mode (SMIF in SCMR = 0) MPIE TEIE CKE[1:0]...
Page 629 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface CKE[1:0] Bits (Clock Enable) These bits select the clock source and SCKn pin function. TEIE Bit (Transmit End Interrupt Enable) Enables or disables a TEI interrupt request. A TEI interrupt request is disabled by clearing the TEIE bit to 0. MPIE Bit (Multi-Processor Interrupt Enable) When this bit is set to 1 and the data with the multi-processor bit set to 0 is received, the data is not read and setting the status flags ORER and FER in SSR to 1 is disabled.
Page 630 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface (2) Smart Card Interface Mode (SMIF in SCMR = 1) MPIE TEIE CKE[1:0] Value after reset: Symbol Bit Name Description b1, b0 CKE[1:0] Clock Enable • When GM in SMR = 0 R/W* b1 b0 0 0: Output disabled (The SCKn pin is available for use as an I/...
Page 631 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface TE Bit (Transmit Enable) Enables or disables serial transmission. When this bit is set to 1, serial transmission is started by writing transmit data to TDR. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format.
Page 632: Serial Status Register (Ssr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2.7 Serial Status Register (SSR) Note: • Some bits in SSR have different functions in serial communications interface mode and smart card interface mode. (1) Serial Communications Interface Mode (SMIF in SCMR = 0) —...
Page 633 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface PER Bit (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] • When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 634 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface (2) Smart Card Interface Mode (SMIF in SCMR = 1) — — ORER TEND MPBT Value after reset: x: Undefined Symbol Bit Name Description MPBT Multi-Processor Bit Transfer This bit should be set to 0 in smart card interface mode. Multi-Processor This bit is not used in smart card interface mode.
Page 635 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] • When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 636: Smart Card Mode Register (Scmr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2.8 Smart Card Mode Register (SCMR) BCP2 — — — SDIR SINV — SMIF Value after reset: Symbol Bit Name Description SMIF Smart Card Interface Mode 0: Serial communications interface mode R/W* Select 1: Smart card interface mode...
Page 637: Bit Rate Register (Brr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2.9 Bit Rate Register (BRR) Value after reset: BRR is an 8-bit register that adjusts the bit rate. As each SCI channel has independent baud-rate generator control, different bit rates can be set for each. Table 15.4 lists the relationships between the setting (N) in the BRR and the bit rate (B) for normal asynchronous mode, multi-processor transfer, clock synchronous mode, and smart card interface mode.
Page 638 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Table 15.6 Base Clock Settings in Smart Card Interface Mode SCMR Setting SMR Setting Base Clock Cycles for BCP2 Bit BCP[1:0] Bits One-bit Period 93 clock cycles 128 clock cycles 186 clock cycles 512 clock cycles 32 clock cycles...
Page 639 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Table 15.8 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) P1φ (MHz) Maximum Bit Rate(bps) 1562500 2000000 66.67 2083333 Note: • When the ABCS bit in SEMR is set to 1, the bit rate is two times. Table 15.9 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Maximum Bit Rate(bps)
Page 640 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Table 15.12 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) P1φ (MHz) 66.67 Bit Rate (bps) Error (%) Error (%) Error (%) 9600 0.01 0.44...
Page 641: Serial Extended Mode Register (Semr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2.10 Serial Extended Mode Register (SEMR) — — NFEN ABCS — — — — Value after reset: Symbol Bit Name Description b3 to b0 — Reserved These bits are read as 0. The write value should be 0. ABCS Asynchronous Mode (Valid only in asynchronous mode)
Page 642: Extended Function Control Register (Secr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.2.12 Extended Function Control Register (SECR) — — — — — — CTSE — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. CTSE CTS Enable 0: CTS pin function is disabled (RTS output function is enabled).
Page 643: Operation In Asynchronous Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.3 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communications. One frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the communications line is usually held in the mark state (high level).
Page 644 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Table 15.14 Serial Transfer Formats (Asynchronous Mode) SMR Setting Serial Transfer Format and Frame Length 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP...
Page 645: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times* the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Page 646: Clock
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.3.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be selected as the SCI’s transfer clock, according to the setting of the CM bit in SMR and the CKE[1:0] bits in SCR. When an external clock is input to the SCKn pin, the clock frequency should be 16 times the bit rate (when ABCS in SEMR = 0) and 8 times the bit rate (when ABCS in SEMR = 1).
Page 647: Sci Initialization (Asynchronous Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.3.5 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, start by writing the initial value “00h” to SCR and then continue through the procedure for SCI given in the sample flowchart (Figure 15.5). Whenever the operating mode or transfer format is changed, SCR must be initialized before the change is made.
Page 648: Serial Data Transmission (Asynchronous Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.3.6 Serial Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for serial transmission in asynchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI transfers data from TDR to TSR when data is written to TDR in the TXI interrupt processing routine. The TXI interrupt request at the beginning of transmission is generated when the TE bit in SCR is set to 1 after the TIE bit in SCR is set to 1 or when these two bits are set to 1 simultaneously by a single instruction.
Page 649 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface [ 1 ] [ 1 ] Initialization: Initialization The TXDn automatically becomes the output pin for data being transmitted. Start data transmission After the TE bit in SCR is set to 1, 1 is output for a frame, and transmission is enabled.
Page 650: Serial Data Reception (Asynchronous Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.3.7 Serial Data Reception (Asynchronous Mode) Figure 15.8 and Figure 15.9 show examples of the operation for serial data reception in asynchronous mode. In serial data reception, the SCI operates as described below. 1.
Page 651 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Data Data Data Parity Stop Parity Stop Start bit Start bit Start bit Idle state (mark state) RXI interrupt flag SSR.FER flag RDR data read in RXI interrupt RXI interrupt processing routine request generated...
Page 652 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface [ 1 ] Initialization [ 1 ] Initialization: Start data reception The RXDn automatically becomes the input pin for data being received. [ 2 ] [ 3 ] Receive error processing and break [ 2 ] Read ORER, PER, and FER flags in SSR detection:...
Page 653 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface [ 3 ] Error processing SSR.ORER flag = 1 Overrun error processing* [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 654: Multi-Processor Communications Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.4 Multi-Processor Communications Function Using the multi-processor communication functions enables to transmit and receive data by sharing a communication line between multiple processors by using asynchronous serial communication in which the multi-processor bit is added. In multi-processor communication, a unique ID code is allocated to each receiving station.
Page 655: Multi-Processor Serial Data Transmission
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.4.1 Multi-Processor Serial Data Transmission Figure 15.13 is a sample flowchart of multi-processor data transmission. In the ID transmission cycle, the ID should be transmitted with the MPBT bit in SSR set to 1. In the data transmission cycle, the data should be transmitted with the MPBT bit set to 0.
Page 656: Multi-Processor Serial Data Reception
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.4.2 Multi-Processor Serial Data Reception Figure 15.15 and Figure 15.16 are sample flowcharts of multi-processor data reception. When the MPIE bit in SCR is set to 1, reading the communication data is skipped until reception of the communication data in which the multi- processor bit is set to 1.
Page 657 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Initialization [ 1 ] [ 1 ] Initialization: The RXDn automatically becomes the input pin for data being received. Start data reception [ 2 ] ID reception cycle: Set the MPIE bit in SCR to 1 and wait for ID [ 2 ] Set MPIE bit in SCR to 1.
Page 658 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface [ 5 ] Error processing SSR.ORER flag = 1 Overrun error processing* [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 659: Operation In Clock Synchronous Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.5 Operation in Clock Synchronous Mode Figure 15.17 shows the data format for clock synchronous serial data communications. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data.
Page 660: Initialization (Clock Synchronous Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface [Conditions for low-level output] Satisfaction of all conditions listed below • The value of the RE or TE bit in the SCR is 1 • Neither transmission nor reception is in progress •...
Page 661: Serial Data Transmission (Clock Synchronous Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.5.4 Serial Data Transmission (Clock Synchronous Mode) Figure 15.19 shows an example of the operation for serial transmission in clock synchronous mode. In serial data transmission, the SCI operates as described below. 1.
Page 662 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface [ 1 ] Initialization [ 1 ] Initialization: The TXDn automatically becomes the output pin for data being transmitted. Start transmission [ 2 ] Writing transmit data write to TDR by a TXI interrupt request: [ 2 ] When transmit data is transferred from TDR to TSR, a...
Page 663: Serial Data Reception (Clock Synchronous Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.5.5 Serial Data Reception (Clock Synchronous Mode) Figure 15.21 and Figure 15.22 show examples of SCI operation for serial reception in clock synchronous mode. In serial data reception, the SCI operates as described below. 1.
Page 664 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Synchronization clock Serial data Bit 6 Bit 7 Bit 0 Bit 7 Bit 0 RXI interrupt flag SSR.ORER flag RXI interrupt RXI interrupt RDR data read in RXI RDR data read in RXI request request interrupt processing...
Page 665 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Initialization [ 1 ] [ 1 ] Initialization: Make input port-pin settings for pins to be used as RXDn pins. Start data reception [ 2 ] [ 3 ] Receive error processing: If a receive error occurs, read the ORER flag in [ 2 ] Read ORER flag in SSR...
Page 666: Simultaneous Serial Data Transmission And Reception (Clock Synchronous Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.5.6 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) Figure 15.24 shows a sample flowchart for simultaneous serial transmit and receive operations in clock synchronous mode. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 667: Operation In Smart Card Interface Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.6 Operation in Smart Card Interface Mode The SCI supports the smart card (IC card) interface conforming to the ISO/IEC 7816-3 (Identification Card) standard. Smart card interface mode can be selected using the appropriate register. 15.6.1 Sample Connection Figure 15.25 shows a sample connection between a smart card (IC card) and this LSI.
Page 668: Data Format (Except In Block Transfer Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.6.2 Data Format (Except in Block Transfer Mode) Figure 15.26 shows the data transfer formats in smart card interface mode. • One frame consists of 8-bit data and a parity bit in asynchronous mode. •...
Page 669 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface (1) Direct Convention Type For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in Figure 15.27. Therefore, data in the start character in the figure is 3Bh. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR.
Page 670: Block Transfer Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.6.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. • Even if a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next frame.
Page 671: Initialization (Smart Card Interface Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 372 clock cycles 372 clock cycles 186 clock cycles 186 clock cycles 371 0 Internal base clock Start bit Receive data (RXDn) Synchronization sampling timing Data sampling timing Figure 15.29 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) 15.6.5...
Page 672: Serial Data Transmission (Except In Block Transfer Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.6.6 Serial Data Transmission (Except in Block Transfer Mode) Serial data transmission in smart card interface mode (except in block transfer mode), in that an error signal is sampled and data can be re-transmitted, is different from that in normal serial communications interface mode. Figure 15.30 shows the data retransfer operation during transmission.
Page 673 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Note that the SSR.TEND flag is set in different timings depending on the GM bit setting in SMR. Figure 15.31 shows the SSR.TEND flag generation timing. SSR.TEND flag Guard (TXI interrupt) time 12.5 etu (11.5 etu in block transfer mode) When GM bit in SMR = 0...
Page 674 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Start Initialization Start data transmission SSR.ERS flag = 0? Error processing TXI interrupt Write transmit data to TDR Write all transmit data SSR.ERS flag = 0? Error processing TXI interrupt Clear bits TIE, RIE, and TE in SCR to 0 Figure 15.32...
Page 675: Serial Data Reception (Except In Block Transfer Mode)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.6.7 Serial Data Reception (Except in Block Transfer Mode) Serial data reception in smart card interface mode is similar to that in serial communications interface mode. Figure 15.33 shows the data retransfer operation in reception mode. 1.
Page 676: Clock Output Control
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Start Initialization Start data reception SSR.ORER = 0 and SSR.PER = 0? Error processing RXI interrupt Read data from RDR All data received? Clear bits RIE and RE in SCR to 0 Figure 15.34 Sample Smart Card Interface Reception Flowchart 15.6.8...
Page 677 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. (1) At Power-On To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1.
Page 678: Noise Cancellation Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.7 Noise Cancellation Function Figure 15.37 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of two stages of flip-flop circuits and a match-detection circuit. When the level on the pin matches in three consecutive samples taken at the set sampling interval, the matching level continues to be conveyed internally until the level on the pin again matches in three consecutive samples.
Page 679: Interrupt Sources
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.8 Interrupt Sources 15.8.1 Interrupts in Serial Communications Interface Mode Table 15.16 lists interrupt sources in serial communication interface mode. Individual interrupt sources can be enabled or disabled with the enable bits in SCR. If the SCR.TIE bit is 1, a TXI interrupt request is generated when data for transmission are transferred from the TDR to the TSR.
Page 680: Interrupts In Smart Card Interface Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.8.2 Interrupts in Smart Card Interface Mode Table 15.17 lists interrupt sources in smart card interface mode. A transmit end interrupt (TEI) request cannot be used in this mode. Table 15.17 Interrupt Sources Name Interrupt Source...
Page 681: Usage Notes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.9 Usage Notes 15.9.1 Setting the Module Standby Function SCI operation can be started and stopped by setting the module standby mode. With the value after a reset, SCI operations are stopped. The registers of the modules only become accessible after release from the module standby state. For details, refer to section 42, Power-Down Modes.
Page 682: Sci Operations During Low Power Consumption State
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.9.9 SCI Operations during Low Power Consumption State (1) Transmission When making settings for the module standby state or in transitions to software standby, stop operations (by setting the TIE, TE, and TEIE bits in the SCR to 0) after switching the TXDn pin to the general-purpose I/O port pin function. Clearing the TE bit in SCR to 0 resets the TSR and the TEND bit in the SSR.
Page 683 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface Figure 15.39 shows a sample flowchart for transition to software standby mode during reception. <Data transmission> [ 1 ] Data being transmitted is lost halfway. Data can be [ 1 ] All data transmitted? normally transmitted from the CPU by setting the TE bit in SCR to 1, reading SSR, and writing data to...
Page 684: External Clock Input In Clock Synchronous Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface <Data reception> [ 1 ] Data being received is invalid. [ 1 ] RXI interrupt Read receive data in RDR SCR.RE = 0 Make transition to software standby mode [ 2 ] Setting for the module standby state is [ 2 ] included.
Page 685: 15.10 Irda Communications
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.10 IrDA Communications In combination with the on-chip IrDA module, the channel 0 serial communications interface (SCI) transmits and receives waveforms conforming with version 1.0 of the Infrared Data Association (IrDA) standard. When the IrDA function is enabled by the IRE bit in the IRCR register, the SCI_TXD0 and SCI_RXD0 signals transmitted and received on channel 0 are encoded to and decoded from waveforms conforming with the standard.
Page 686: 15.11 Irda Register Description
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.11 IrDA Register Description Table 15.19 shows the register configuration. Table 15.19 Register Configuration Register Name Abbreviation Initial Value Address Access Size IrDA control register IRCR H’00 H'E8014000 15.11.1 IrDA Control Register (IRCR) IRCR is the register which sets the operation of the IrDA module.
Page 687: 15.12 Irda Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.12 IrDA Operation 15.12.1 Flow of IrDA Setting To set the operation of the IrDA module, follow the procedure below. 1. Make the general-purpose I/O port settings. 2. Set the IRCR register. 3.
Page 688: Reception
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.12.3 Reception In reception with the IRDA function enabled, IR frame data from the SCI_RXD0 pin are converted to serial data and output to the RXD pin for the SCI. When the IRRXINV bit is 0, a bit with the value 0 is output on the detection of a high- level pulse.
Page 689: 15.13 Notes On Using The Irda Module
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 15. Serial Communications Interface 15.13 Notes on Using the IrDA Module 15.13.1 Shortest Pulse Width in Reception Pulses shorter than the lower limit (1.41 μs) are not recognized. 15.13.2 Asynchronous Basic Clock for Serial Communication Interface The IrDA module receives the basic clock with a frequency which is 16 times as high as the communication bit rate from the SCI and operates in combination with the clock.
Page 690: Renesas Serial Peripheral Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface Renesas Serial Peripheral Interface This LSI circuit includes three independent Renesas serial peripheral interfaces. This module is capable of full-duplex synchronous serial communication. 16.1 Features This module has the following features.
Page 691 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface • Others Provides loop back mode Provides a function for disabling (initializing) this module Peripheral bus Module data bus SPRX SPCR SPBR SPTX (FIFO (FIFO SSLP structure) structure) SPPCR...
Page 692: Input/Output Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.2 Input/Output Pins Table 16.1 shows the pin configuration. This module automatically switches the input/output direction of the SSL pin. SSL is set as an output in master mode and as an input in slave mode. Pins RSPCK, MOSI, and MISO are automatically set as inputs or outputs according to the setting of master or slave and the level input on SSL (see section 16.4.2, Pin...
Page 693: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3 Register Descriptions Table 16.2 shows the register configuration. These registers enable this module to perform the following controls: specifying master/slave modes, specifying a transfer format, and controlling the transmitter and receiver.
Page 694 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface Table 16.2 Register Configuration Initial Access Channel Register Name Abbreviation* Value Address Size Control register_2 SPCR_2 H'00 H'E800D800 Slave select polarity register_2 SSLP_2 H'00 H'E800D801 Pin control register_2 SPPCR_2...
Page 695: Control Register (Spcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.1 Control Register (SPCR) SPCR sets the operating mode. If the MSTR and MODFEN bits are changed while the function of this module is enabled by setting the SPE bit to 1, subsequent operations cannot be guaranteed.
Page 696: Slave Select Polarity Register (Sslp)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.2 Slave Select Polarity Register (SSLP) SSLP sets the polarity of the SSL signal. If the contents of SSL0P are changed while the function of this module is enabled by setting the SPE bit in the control register (SPCR) to 1, subsequent operations cannot be guaranteed.
Page 697: Status Register (Spsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.4 Status Register (SPSR) SPSR indicates the operating status. Bit: ⎯ ⎯ ⎯ SPRF TEND SPTEF MODF OVRF Initial value: R/W: R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag after reading 1.
Page 698 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface Bit Name Initial Value R/W Function MODF R/(W)* Mode Fault Error Flag Indicates the occurrence of a mode fault error. If the MODFEN bit is set to 1 when this module is in slave mode and the SSL pin is negated before the RSPCK cycle necessary for data transfer ends, this module detects a mode fault error.
Page 699: Data Register (Spdr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.5 Data Register (SPDR) SPDR is a buffer that holds data for transmission and reception. The transmit buffer (SPTX) and receive buffer (SPRX) are independent and are mapped to SPDR.
Page 700: Sequence Status Register (Spssr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.7 Sequence Status Register (SPSSR) SPSSR indicates the sequence control status when this module operates in master mode. Bit: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SPCP1 SPCP0 Initial value:...
Page 701: Data Control Register (Spdcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface Table 16.3 Relationship between SPBR and BRDV1 and BRDV0 Settings Bit Rate SPBR (n) BRDV[1:0] (N) Division Ratio P1φ = 50 MHz P1φ = 64 MHz P1φ = 66.67 MHz 25.00 Mbps...
Page 702: Clock Delay Register (Spckd)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.10 Clock Delay Register (SPCKD) SPCKD sets a period from the beginning of SSL signal assertion to RSPCK oscillation (RSPCK delay) when the SCKDEN bit in the command register (SPCMD) is 1. If the contents of SPCKD are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be guaranteed.
Page 703: Slave Select Negation Delay Register (Sslnd)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.11 Slave Select Negation Delay Register (SSLND) SSLND sets a period (SSL negation delay) from the transmission of a final RSPCK edge to the negation of the SSL signal during a serial transfer by this module in master mode. If the contents of SSLND are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be guaranteed.
Page 704: Next-Access Delay Register (Spnd)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.12 Next-Access Delay Register (SPND) SPND sets a non-active period (next-access delay) after termination of a serial transfer when the SPNDEN bit in the command register (SPCMD) is 1. If the contents of SPND are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be guaranteed.
Page 705: Command Register (Spcmd)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.13 Command Register (SPCMD) Each channel has four command registers (SPCMD0 to SPCMD3). SPCMD0 to SPCMD3 are used to set a transfer format for master mode operation. Some of the bits in SPCMD0 are used to set a transfer mode for slave mode operation.
Page 706 CPOL RSPCK Polarity Setting Sets an RSPCK polarity in master or slave mode. When data communication is performed between the Renesas serial peripheral interface module and the other modules, the same RSPCK polarity should be set for both modules. 0: RSPCK = 0 when idle...
Page 707: Buffer Control Register (Spbfcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.14 Buffer Control Register (SPBFCR) SPBFCR resets the number of data units in the transmit buffer (SPTX) or receive buffer (SPRX) and sets the number of triggering data units.
Page 708: Buffer Data Count Setting Register (Spbfdr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.3.15 Buffer Data Count Setting Register (SPBFDR) SPBFDR indicates the number of data units stored in the transmit buffer (SPTX) and receive buffer (SPRX). The upper eight bits indicate the number of transmit data units in SPTX and the lower eight bits indicate the number of receive data units in SPRX.
Page 709: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.4 Operation In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the final valid data. 16.4.1 Overview of Operations This module is capable of serial transfers in slave mode and master mode.
Page 710: Pin Control
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.4.2 Pin Control According to the MSTR bit in the control register (SPCR), this module can automatically switch pin directions and output modes. Table 16.5 shows the relationship between pin states and bit settings.
Page 711 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (2) Master/Slave (with This LSI Acting as Slave) Figure 16.3 shows a master/slave system configuration example when this LSI is used as a slave. When this LSI is to operate as a slave, the SSL pin is used as SSL input.
Page 712 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (3) Master/Multi-Slave (with This LSI Acting as Slave) Figure 16.5 shows a master/multi-slave system configuration example when this LSI is used as a slave. In the example of Figure 16.5, the system is comprised of a master and two LSIs (slave X and slave Y).
Page 713: Transfer Format
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.4.4 Transfer Format (1) CPHA = 0 Figure 16.6 shows a sample transfer format for the serial transfer of 8-bit data when the CPHA bit in the command register (SPCMD) is 0. In Figure 16.6, RSPCK (CPOL = 0) indicates the RSPCK signal waveform when the CPOL bit in SPCMD is 0;...
Page 714 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (2) CPHA = 1 Figure 16.7 shows a sample transfer format for the serial transfer of 8-bit data when the CPHA bit in the command register (SPCMD) is 1. In Figure 16.7, RSPCK (CPOL = 0) indicates the RSPCK signal waveform when the CPOL bit in SPCMD is 0;...
Page 715: Data Format
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.4.5 Data Format The data format depends on the settings in the command register (SPCMD). Irrespective of MSB/LSB first, this module treats the range from the LSB of the data register (SPDR) to the assigned data length as transfer data.
Page 716 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (2) MSB First Transfer (16-Bit Data) Figure 16.9 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs a 16-bit data length MSB-first data transfer.
Page 717 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (3) MSB First Transfer (8-Bit Data) Figure 16.10 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs an 8- bit data length MSB-first data transfer.
Page 718 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (4) LSB First Transfer (32-Bit Data) Figure 16.11 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs a 32- bit data length LSB-first data transfer.
Page 719 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (5) LSB First Transfer (16-Bit Data) Figure 16.12 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs a 16- bit data length LSB-first data transfer.
Page 720 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (6) LSB First Transfer (8-Bit Data) Figure 16.13 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs an 8- bit data length LSB-first data transfer.
Page 721: Error Detection
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.4.6 Error Detection In the normal serial transfer, the data written to the transmit buffer of the data register (SPDR) is serially transmitted, and the serially received data can be read from the receive buffer of SPDR. If access is made to SPDR, depending on the status of the transmit buffer/receive buffer or the status at the beginning or end of serial transfer, in some cases non- normal transfers can be executed.
Page 722 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (1) Overrun Error If serial transfer ends when the receive buffer of the data register (SPDR) is full, this module detects an overrun error, and sets the OVRF bit in SPSR to 1. When the OVRF bit is 1, this module does not copy data from the shift register to the receive buffer so that the data prior to the occurrence of the error is retained in the receive buffer.
Page 723: Initialization
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (2) Mode Fault Error When the MSTR bit is 0, this module operates in slave mode. This module detects a mode fault error if the SSL input signal is negated during the serial transfer period (from the time the driving of valid data is started to the time the final valid data is fetched) when the MODFEN bit is 1 in slave mode.
Page 724: Spi Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.4.8 SPI Operation (1) Multi-Master Mode Operation This section explains the operation in multi-master mode. (a) Starting Serial Transfer A serial transfer is started when transmit data is copied from the transmit buffer to the shift register, the shift register becomes full, and the receive buffer has a space for the receive data length.
Page 725 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface Determine transfer Sequence determined Refer to SCKD, SSLND, and SPND (if necessary) format SPSCR SPCMD0 SCKD SSLND SPND SPCMD1 Pointer H'02 H'01 H'00 H'02 SPCP1 SPCMD2 and SPCP 0...
Page 726 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface not used. Even when the CPHA bit in SPCMD is 0, this module can accurately start serial transfers by asserting the SSL signal for the next transfer. For this reason, burst transfers in master mode can be executed irrespective of CPHA bit settings (see section 16.4.8 (2), Slave Mode Operation).
Page 727 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (g) Next-Access Delay (t3) The next-access delay value in master mode depends on SPNDEN bit settings in the command register (SPCMD) and on next-access delay register (SPND) settings. This module determines the SPCMD to be referenced during serial transfer by pointer control, and determines a next-access delay value during serial transfer by using the SPNDEN bit in the selected SPCMD and SPND, as shown in Table 16.10.
Page 728 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (h) Initialization Flowchart Figure 16.17 is a flowchart illustrating an example of initialization in SPI operation when this module is used in master mode. For a description of how to set up the interrupt controller, direct memory access controller, and input/output ports, see the descriptions given in the individual blocks.
Page 729 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface Transfer Operation Flowchart Figure 16.18 is a flowchart illustrating a transfer in SPI operation when this module is used in master mode. End of initialization in master mode Transmit buffer...
Page 730 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (2) Slave Mode Operation (a) Starting Serial Transfer If this module detects an SSL input signal assertion when the CPHA bit in the command register 0 (SPCMD0) is 0, this module is required to start driving valid data to the MISO output signal.
Page 731 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (e) Initialization Flowchart Figure 16.19 is a flowchart illustrating an example of initialization in SPI operation when this module is used in slave mode. For a description of how to set up the interrupt controller, direct memory access controller, and input/output ports, see the descriptions given in the individual blocks.
Page 732 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface Transfer Operation Flowchart (CPHA = 0) Figure 16.20 is a flowchart illustrating a transfer in SPI operation when this module is used in slave mode with the CPHA bit in the command register 0 (SPCMD0) set to 0.
Page 733 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface (g) Transfer Operation Flowchart (CPHA = 1) Figure 16.21 is a flowchart illustrating a transfer in SPI operation when this module is used in slave mode with the CPHA bit in the command register 0 (SPCMD0) and the MODFEN bit in the control register (SPCR) set to 1, respectively.
Page 734: Error Handling
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.4.9 Error Handling Figure 16.22 and Figure 16.23 show the error handling. The following error handling is used to return from the error state after an error in master or slave mode.
Page 735: Loopback Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 16. Renesas Serial Peripheral Interface 16.4.10 Loopback Mode When 1 is written to the SPLP bit in the pin control register (SPPCR), this module shuts off the path between the MISO pin and the shift register, and between the MOSI pin and the shift register, and connects the input path and the output path (reversed) of the shift register.
Page 736: Spi Multi I/O Bus Controller
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller SPI Multi I/O Bus Controller The SPI multi I/O bus controller outputs control signals to the serial flash memory connected to the SPI multi I/O bus space, thus enabling direct connection of the serial flash memory. This LSI incorporates an independent SPI multi I/O bus controller channel.
Page 737: Block Diagram
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.2 Block Diagram Figure 17.1 shows a block diagram of this module for one channel. Internal bus Bus interface Control register Transmit data Read cache buffer Module data bus Transmit data Receive data Transmission/...
Page 738: Input/Output Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.3 Input/Output Pins Table 17.1 shows the pin configuration for one channel. Table 17.1 Pin Configuration Port Pin Name Symbol Function Common Clock pin SPBCLK_n Output Clock output Slave select pin SPBSSL_n Output...
Page 739: Register Descriptions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4 Register Descriptions Table 17.2 shows the register configuration. Table 17.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size Common control register_0 CMNCR_0 H'01AA4000 H'3FEFA000 SSL delay register_0 SSLDR_0 H'00070707...
Page 740: Common Control Register (Cmncr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the SPI multi I/O bus controller. The settings of this register are reflected both in external address space read mode and SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1;...
Page 741 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller Initial Bit Name Value Description 17, 16 MOIIO0[1:0] SPBSSL Output Idle Value Fix SPBIO00, SPBIO01 Fixes output values of SPBIO00 and SPBIO01 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is Hi-Z, if Hi-Z was the state in the immediately previous bit period).
Page 742 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller Initial Bit Name Value Description SSLP SPBSSL Signal Polarity Sets the polarity of SPBSSL signal. 0: Active low SPBSSL signal 1: Active high SPBSSL signal CPOL SPBSSL Negation Period SPBCLK Output Direction Sets the SPBCLK output direction during SPBSSL negation period.
Page 743: Ssl Delay Register (Ssldr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.2 SSL Delay Register (SSLDR) SSLDR is a 32-bit register that adjusts the timing between the SPBSSL signal and the SPBCLK signal. The settings of this register are reflected both in external address space read mode and SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1;...
Page 744: Bit Rate Register (Spbcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.3 Bit Rate Register (SPBCR) SPBCR is a 32-bit register that sets the bit rate. The settings of this register are reflected both in external address space read mode and SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1;...
Page 745 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller (1) Bit Rate SPBR[7:0] and BRDV[1:0] are used for setting the bit rate. The following formula is used to calculate the bit rate when SPBR[7:0] ≠ 0. Bit rate = Bφ / (2 × n × 2 n: SPBR[7:0] setting (1, …, 255) N: BRDV[1:0] setting (0 to 3) Also the following formula is used to calculate the bit rate when SPBR[7:0] = 0.
Page 746: Data Read Control Register (Drcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.4 Data Read Control Register (DRCR) DRCR is a 32-bit register that sets the operation in external address space read mode. The bits except the SSLN bit should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed.
Page 747: Data Read Command Setting Register (Drcmr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.5 Data Read Command Setting Register (DRCMR) DRCMR is a 32-bit register that sets the commands issued in external address space read mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed.
Page 748: Data Read Extended Address Setting Register (Drear)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.6 Data Read Extended Address Setting Register (DREAR) DREAR is a 32-bit register that sets the address when the serial flash address is output in 32-bit mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed.
Page 749: Data Read Option Setting Register (Dropr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.7 Data Read Option Setting Register (DROPR) DROPR is a 32-bit register that sets the option data in external address space read mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed.
Page 750: Data Read Enable Setting Register (Drenr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.8 Data Read Enable Setting Register (DRENR) DRENR is a 32-bit register that sets the bit size of the command, optional command, address, option data, and read data in external address space read mode and enables outputting them other than read data.
Page 751 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller Initial Bit Name Value Description Command Enable Sets the command to be output. 0: Command output disabled 1: Command output enabled ― Reserved This bit is always read as 0. The write value should always be 0. OCDE Optional Command Enable Sets the optional command to be output.
Page 752: Spi Mode Control Register (Smcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.9 SPI Mode Control Register (SMCR) SMCR is a 32-bit register that sets the operation in SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed.
Page 753: Spi Mode Command Setting Register (Smcmr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.10 SPI Mode Command Setting Register (SMCMR) SMCMR is a 32-bit register that sets the commands issued in SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed.
Page 754: Spi Mode Option Setting Register (Smopr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.12 SPI Mode Option Setting Register (SMOPR) SMOPR is a 32-bit register that sets the option data in SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed.
Page 755: Spi Mode Enable Setting Register (Smenr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.13 SPI Mode Enable Setting Register (SMENR) SMENR is a 32-bit register that sets the bit size of the command, optional command, address, option data, and transfer data in SPI operating mode and enables their output. SMENR also enables dummy cycle insertion. Disabling all of the command, optional command, address, option data, dummy cycle, and transfer data is prohibited.
Page 756 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller Initial Bit Name Value Description Dummy Cycle Enable Enables insertion of the dummy cycle before the read data. Note: Dummy cycle insertion is prohibited for write in SPI operating mode including the case in which a transfer ends with a dummy cycle.
Page 757: Spi Mode Read Data Register 0 (Smrdr0)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.14 SPI Mode Read Data Register 0 (SMRDR0) SMRDR0 is a 32-bit register that stores the read data in SPI operating mode. Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR).
Page 758: Spi Mode Write Data Register 0 (Smwdr0)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.16 SPI Mode Write Data Register 0 (SMWDR0) SMWDR0 is a 32-bit register that sets the write data in SPI operating mode. Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR).
Page 759: Common Status Register (Cmnsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.18 Common Status Register (CMNSR) CMNSR is a 32-bit register that holds flags indicating the operating state. The settings of this register are reflected both in external address space read mode and SPI operating mode. Bit: Initial value: R/W:...
Page 760: Spi Ac Input Characteristics Adjustment Register (Ckdly) (Rz/A1Lu Only)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.19 SPI AC Input Characteristics Adjustment Register (CKDLY) (RZ/A1LU only) CKDLY is used to adjust the timing of the setup and hold times for data input. The timing should be adjusted to suit the AC characteristics of the serial flash memory to be connected.
Page 761: Data Read Dummy Cycle Setting Register (Drdmcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.20 Data Read Dummy Cycle Setting Register (DRDMCR) DRDMCR is a 32-bit register that sets the size and number of dummy cycles to be inserted in external address space read mode.
Page 762: Data Read Ddr Enable Register (Drdrenr) (Rz/A1Lu Only)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.21 Data Read DDR Enable Register (DRDRENR) (RZ/A1LU only) DRDRENR is a 32-bit register that sets SDR or DDR transfer of the address, option data, and read data in external address space read mode.
Page 763: Spi Mode Dummy Cycle Setting Register (Smdmcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.22 SPI Mode Dummy Cycle Setting Register (SMDMCR) SMDMCR is a 32-bit register that sets the size and number of dummy cycles to be inserted in SPI operating mode. The settings of this register are enabled when the DME bit in the SPI mode enable setting register (SMENR) is 1.
Page 764: Spi Mode Ddr Enable Register (Smdrenr) (Rz/A1Lu Only)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.23 SPI Mode DDR Enable Register (SMDRENR) (RZ/A1LU only) SMDRENR is a 32-bit register that sets SDR or DDR transfer of the address, option data, and transfer data in SPI operating mode.
Page 765: Spi Ac Output Characteristics Adjustment Register (Spodly) (Rz/A1Lu Only)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.4.24 SPI AC Output Characteristics Adjustment Register (SPODLY) (RZ/A1LU only) SPODLY is used to adjust the timing of the delay, hold, buffer on and buffer off times for data output. The timing should be adjusted to suit the AC characteristics of the serial flash memory to be connected.
Page 766: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5 Operation 17.5.1 System Configuration With this module, one or two serial flash memories can be directly connected per channel (data size of 1, 2, and 4 bits). The number of connected memories can be selected using the BSZ[1:0] bits in CMNCR.
Page 767: Address Map
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.2 Address Map In external address space read mode, the serial flash connected is assigned in the SPI multi I/O bus space. A maximum accessible address space differs depending on the number of serial flash memories connected. In combination with DREAR, a maximum of 4 Gbytes can be accessed when one serial flash memory is connected, and a maximum of 8 Gbytes can be accessed when two memories are connected.
Page 768: Data Alignment
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.4 Data Alignment Data alignment can be set by using the SFDE bit in the common control register (CMNCR). Data alignment in data read mode and in SPI mode are shown in Figure 17.5 and Figure 17.6, respectively. When two serial flash memories are connected, the serial flash memory connected to the pin SPBIO30-SPBIO00 has the address 2n and the serial flash memory connected to the pin SPBIO31-SPBIO01 has the address 2n + 1.
Page 769: Operating Modes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.5 Operating Modes This module has two operating modes: external address space read mode and SPI operating mode. In external address space read mode, a read access to the SPI multi I/O bus space is converted into SPI communication and data is received.
Page 770 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller SPI multi I/O bus space access SPBSSL SPBCLK SPBMO0 Command Address SPBMI0 Read data 8/16/32 bits Flags SSLF bit TE ND bit Figure 17.7 Normal Read Operation Timing R01UH0437EJ0600 Rev.6.00 17-35 Jan 29, 2021...
Page 771 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller (2) Burst Read Operation When the RBE bit in DRCR is set to 1, burst read operation is performed. Read cache is enabled in the burst read operation. For read cache operation, see section 17.5.7, Read Cache. For reading bytes, words, or longwords, the read cache is first referred to for the data.
Page 772 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller SPI multi I/O bus space access SPBSSL SPBCLK SPBMO0 Comma nd Address Read data Read data SPBMI0 64 bits 64 bits × RBU RST (read burst len gth) bits Flags SSLF bit TEND bit...
Page 773 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller (4) Initial Setting Flow An example of an initial setting flow in external address space read mode is shown in Figure 17.12. External address space read mode Initial setting start Set CKDLY and SPODLY.
Page 774: Read Cache
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.7 Read Cache This module has a simple built-in read cache. The read cache can be used during external address space read mode and burst read operation. The read cache is configured with a line size of 64 bits and 16 entries. Read cache configuration is shown in Figure 17.13.
Page 775: Spi Operating Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.8 SPI Operating Mode This module can carry out an arbitrary SPI operation by using the register settings. The transfer format is determined based on the following registers. - Common control register (CMNCR) - SSL delay register (SSLDR) - Bit rate setting register (SPBCR)
Page 776 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller (3) Retention of SPBSSL Pin Assertion By setting the SSLKP bit in SMCR to 1, assertion of the SPBSSL pin can be continued till the next transfer. With this function, the transfer can be carried out continuously with the SPBSSL kept in the asserted state.
Page 777 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller (5) Data Transfer Setting Flow An example of a data transfer setting flow in SPI operating mode is shown in Figure 17.17. SPI operating mode Initial setting end •...
Page 778: Transfer Format
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.9 Transfer Format (1) SPBSSL Pin Enable Polarity Control The enable polarity of the SPBSSL pin can be changed with the SSLP bit in CMNCR. (2) SPBCLK Output The SPBCLK output direction during SPBSSL negation can be set with the CPOL bit in CMNCR.
Page 779 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller SPBCLK (CPOL = 0) SPBCLK (CPOL = 1) Output pin (CPHAT = 0) Output pin (CPHAT = 1) Sampling (CPHAR = 0) Sampling (CPHAR = 1) SPBSSL (SSLP = 0) SPBSSL (SSLP = 1) Figure 17.19...
Page 780: Data Format
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.10 Data Format This module can input and output data in the order of command, optional command, address, option data, dummy cycle, and data. (1) Data Registers Table 17.5 shows the input and output data. Table 17.5 Data Registers Data...
Page 781 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller Optional Dummy Address Option data Transfer data Command command cycle Data In external address (EAV[7:0]+) read address Data read length OCMD OPD3 OPD2 OPD1 OPD0 DMCYC space read mode In SPI operating OCMD OPD3...
Page 782 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller (3) Bit Size In external address space read mode, the size of the command, optional command, address, option data, and the read data in bit units is respectively controlled with the CDB[1:0], OCDB[1:0], ADB[1:0], OPDB[1:0], and DRDB[1:0] bits in DRENR.
Page 783 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller (b) 2-bit Size When the size is set to 2 bits, SPBIO0_0, SPBIO01, SPBIO10, and SPBIO11 pins will be either the input pins or the output pins. SPBIO20, SPBIO21, SPBIO30, and SPBIO31 pins are not used. Figure 17.23 and Figure 17.24 show the transfer format examples.
Page 784 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 4-bit Size When the size is set to 4 bits, SPBIO00, SPBIO01, SPBIO10, SPBIO11, SPBIO20, SPBIO21, SPBIO30, and SPBIO31 pins will be either the input pins or the output pins. Figure 17.25 and Figure 17.26 show the transfer format examples.
Page 785: Data Pin Control
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.11 Data Pin Control With this module, the status of pins can be automatically changed based on the data size to be used and the read/write settings. The pin status during the SPBSSL negation can be set with the MOIIO3, MOIIO2, MOIIO1, and MOIIO0 bits in CMNCR.
Page 786 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller Table 17.8 Pin Status (3) Transfer Data SPI Operation SPIRE Bit = 0, SPIWE Bit = 1 SPIRE Bit = 1, SPIWE Bit = 1 1-bit Size 2-bit Size 4-bit Size 1-bit Size 2-bit Size...
Page 787: Spbssl Pin Control
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.5.12 SPBSSL Pin Control Negation conditions of the SPBSSL pin are as follows. (1) External Address Space Read Mode (a) Normal read operation (RBE bit in DRCR = 0) SPBSSL negated after completing the data transfer and t2 cycle.
Page 788: Usage Notes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 17. SPI Multi I/O Bus Controller 17.6 Usage Notes 17.6.1 Notes on Transfer to Read Data in SPI Operating Mode If the setting for the bit mode is for division by two or more in SPI operating mode, take note of the following points for caution when setting the SPI mode enable setting register (SMENR) to enable transfer only for reading data.
Page 789: I²C Bus Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface I²C Bus Interface This section gives an overall description of the I C bus interface (RIIC). The first section describes the features specific to this LSI, including the number of channels and the register base addresses.
Page 790: External I/O Signals
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.1.3 External I/O Signals The following table shows the external I/O signals of the RIICn. Table 18.4 RIICn Pin Configuration Channel Multiplexed Pin Name Function RIIC0 RIIC0SCL RIIC0 serial clock I/O pin RIIC0SDA RIIC0 serial data I/O pin RIIC1...
Page 791: Overview
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.2 Overview 18.2.1 Functional Overview Communications format • I C bus format or SMBus format • Master mode or slave mode selectable • Automatic securing of the various set-up times, hold times, and bus-free times for the transfer rate Transfer rate Up to 400 kbps SCL clock...
Page 792 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Arbitration • For multi-master operation – Operation to synchronize the SCL (clock) signal in cases of conflict with the SCL signal from another master is possible. – When issuing the start condition would create conflict on the bus, loss of arbitration is detected by testing for non-matching between the internal signal for the SDA line and the level on the SDA line.
Page 793: Block Diagram
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.2.2 Block Diagram P0φ CKS[2:0] RIICnMR1 BC[2:0] FMPE Output RIICnSCL RIICnBRH Transfer clock control generator RIICnBRL SCLE Noise SCLI canceller RIICnCR1 SCL0, SDA0 NF[1:0] IICRST Transmission/ SDAI reception control ST, RS, SP circuit RIICnCR2 DLCS...
Page 794 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Power supply for pull-up (PVcc) SCLin SCLout# SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Figure 18.2 Connections to the External Circuit by the I/O Pins (I C Bus Configuration Example) RIICnSCL and RIICnSDA are Schmitt input/open-drain output pins for both master and slave...
Page 795: Registers
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3 Registers 18.3.1 RIICnCR1 — I²C Bus Control Register 1 Access: RIICnCR1 is a 32-bit readable/writable register. RIICnCR1L and RIICnCR1H are 16-bit readable/writable registers. RIICnCR1LL, RIICnCR1LH, RIICnCR1HL, and RIICnCR1HH are 8-bit readable/writable registers. Address: RIICnCR1: <RIICn_base>...
Page 796 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Table 18.5 RIICnCR1 register contents (2/2) Bit Position Bit Name Function *1,*2 SDAO SDA Output Control • Read: 0: RIICnSDA pin output is at a low level. 1: RIICnSDA pin is in a high-impedance state. •...
Page 797 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface CAUTION If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information).
Page 798: Riicncr2 - I²C Bus Control Register 2
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.2 RIICnCR2 — I²C Bus Control Register 2 Access: RIICnCR2 is a 32-bit readable/writable register. RIICnCR2L and RIICnCR2H are 16-bit readable/writable registers. RIICnCR2LL, RIICnCR2LH, RIICnCR2HL, and RIICnCR2HH are 8-bit readable/writable registers. Address: RIICnCR2: <RIICn_base>...
Page 799 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface For details on the start condition issuance, see Section 18.12, Start Condition/Restart Condition/ Stop Condition Issuing Function. [Setting condition] When 1 is written to the ST bit [Clearing conditions] • When 0 is written to the ST bit •...
Page 800 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface SP Bit (Stop Condition Issuance Request) This bit is used to request that a stop condition be issued in master mode. When this bit is set to 1 to request to issue a stop condition, a stop condition is issued when the BBSY flag is set to 1 (bus busy) and the MST bit is set to 1 (master mode).
Page 801 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface RIICnCR2.BBSY = 1 and RIICnCR2.MST = 0) • When 1 is written to the RIICnCR1.IICRST bit to apply an RIIC reset or an internal reset MST Bit (Master/Slave Mode) This bit indicates master or slave mode. The RIIC is in slave mode when the MST bit is set to 0 and is in master mode when the bit is set to 1.
Page 802: Riicnmr1 - I²C Bus Mode Register 1
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.3 RIICnMR1 — I²C Bus Mode Register 1 Access: RIICnMR1 is a 32-bit readable/writable register. RIICnMR1L and RIICnMR1H are 16-bit readable/writable registers. RIICnMR1LL, RIICnMR1LH, RIICnMR1HL, and RIICnMR1HH are 8-bit readable/writable registers. Address: RIICnMR1: <RIICn_base>...
Page 803 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface BC[2:0] Bits (Bit Counter) These bits function as a counter that indicates the number of bits remaining to be transferred at the detection of a rising edge on the SCL line. Although these bits are writable and readable, it is not necessary to access these bits under normal conditions.
Page 804: Riicnmr2 - I²C Bus Mode Register 2
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.4 RIICnMR2 — I²C Bus Mode Register 2 Access: RIICnMR2 is a 32-bit readable/writable register. RIICnMR2L and RIICnMR2H are 16-bit readable/writable registers. RIICnMR2LL, RIICnMR2LH, RIICnMR2HL, and RIICnMR2HH are 8-bit readable/writable registers. Address: RIICnMR2: <RIICn_base>...
Page 805 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Table 18.9 RIICnMR2 register contents (2/2) Bit Position Bit Name Function TMOS Timeout Detection Time Selection 0: Long mode is selected. 1: Short mode is selected. Note 1. The setting DLCS = 1 (IIC φ /2) only becomes valid when SCL is at the low level. When SCL is at the high level, the setting DLCS = 1 becomes invalid and the clock source becomes the internal reference clock (IIC φ...
Page 806: Riicnmr3 - I²C Bus Mode Register 3
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.5 RIICnMR3 — I²C Bus Mode Register 3 Access: RIICnMR3 is a 32-bit readable/writable register. RIICnMR3L and RIICnMR3H are 16-bit readable/writable registers. RIICnMR3LL, RIICnMR3LH, RIICnMR3HL, and RIICnMR3HH are 8-bit readable/writable registers. Address: RIICnMR3: <RIICn_base>...
Page 807 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Note 2. The WAIT and RDRFS bits are valid only in receive mode (invalid in transmit mode). NF[1:0] Bits (Noise Filter Stage Selection) These bits are used to select the noise width that can be eliminated for the signal input to RIICnSCL or RIICnSDA pin.
Page 808 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface WAIT Bit (WAIT) This bit is used to control whether to hold the period between the ninth SCL clock cycle and the first SCL clock cycle low until the receive data buffer (RIICnDRR) is completely read each time single- byte data is received in receive mode.
Page 809: Riicnfer - I²C Bus Function Enable Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.6 RIICnFER — I²C Bus Function Enable Register Access: RIICnFER is a 32-bit readable/writable register. RIICnFERL and RIICnFERH are 16-bit readable/writable registers. RIICnFERLL, RIICnFERLH, RIICnFERHL, and RIICnFERHH are 8-bit readable/writable registers. Address: RIICnFER: <RIICn_base>...
Page 810 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface TMOE Bit (Timeout Function Enable) This bit is used to enable or disable the timeout function. For details on the timeout function, see Section 18.13.1, Timeout Function. MALE Bit (Master Arbitration-Lost Detection Enable) This bit is used to specify whether to use the arbitration-lost detection function in master mode.
Page 811: Riicnser - I²C Bus Status Enable Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.7 RIICnSER — I²C Bus Status Enable Register Access: RIICnSER is a 32-bit readable/writable register. RIICnSERL and RIICnSERH are 16-bit readable/writable registers. RIICnSERLL, RIICnSERLH, RRIICnSERHL, and RIICnSERHH are 8-bit readable/writable registers. Address: RIICnSER: <RIICn_base>...
Page 812 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface SARy Bit (Slave Address Register y Enable) (y = 0 to 2) This bit is used to enable or disable the received slave address and the slave address set in RIICnSARy. When this bit is set to 1, the slave address set in RIICnSARy is enabled and is compared with the received slave address.
Page 813: Riicnier - I²C Bus Interrupt Enable Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.8 RIICnIER — I²C Bus Interrupt Enable Register Access: RIICnIER is a 32-bit readable/writable register. RIICnIERL and RIICnIERH are 16-bit readable/writable registers. RIICnIERLL, RIICnIERLH, RIICnIERHL, and RIICnIERHH are 8-bit readable/writable registers. Address: RIICnIER: <RIICn_base>...
Page 814 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface TMOIE Bit (Timeout Interrupt Enable) This bit is used to enable or disable timeout interrupt (INTRIICTMOI) requests when the RIICnSR2.TMOF flag is set to 1. An INTRIICTMOI interrupt request is canceled by clearing the TMOF flag or the TMOIE bit to 0.
Page 815: Riicnsr1 - I²C Bus Status Register 1
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.9 RIICnSR1 — I²C Bus Status Register 1 Access: RIICnSR1 is a 32-bit readable/writable register. RIICnSR1L and RIICnSR1H are 16-bit readable/writable registers. RIICnSR1LL, RIICnSR1LH, RIICnSR1HL, and RIICnSR1HH are 8/1-bit readable/writable registers. Address: RIICnSR1: <RIICn_base>...
Page 816 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface AASy Flag (Slave Address y Detection) (y = 0 to 2) [Setting conditions] <For 7-bit address format: RIICnSARy.FSy = 0> When the received slave address matches the RIICnSARy.SVA[7:1] value with the RIICnSER.SARy bit set to 1 (slave address y detection enabled) This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the frame.
Page 817 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface DID Flag (Device-ID Address Detection) [Setting condition] • When the first frame received immediately after a start condition or restart condition is detected matches a value of (device ID (1111 100 ) + 0 [W]) with the RIICnSER.DIDE bit set to 1 (Device-ID address detection enabled) This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the frame.
Page 818: Riicnsr2 - I²C Bus Status Register 2
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.10 RIICnSR2 — I²C Bus Status Register 2 Access: RIICnSR2 is a 32-bit readable/writable register. RIICnSR2L and RIICnSR2H are 16-bit readable/writable registers. RIICnSR2LL, RIICnSR2LH, RIICnSR2HL, and RIICnSR2HH are 8/1-bit readable/writable registers. Address: RIICnSR2: <RIICn_base>...
Page 819 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface TMOF Flag (Timeout) This flag is set to 1 when the RIIC recognizes timeout after the SCL line state remains unchanged for a certain period. [Setting condition] The timeout function is enabled when the RIICnFER.TMOE bit is 1. It detects an abnormal bus state that the SCL line is held low or high during the following conditions: •...
Page 820 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface • When 1 is written to the RIICnCR1.IICRST bit to apply an RIIC reset or an internal reset Table 18.16 Relationship between Arbitration-Lost Generation Sources and Arbitration- Lost Enable Functions RIICn RIICnFER MALE...
Page 821 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface CAUTION When the NACKF flag is set to 1, the RIIC suspends data transmission/reception. Writing to RIICnDRT in transmit mode or reading from RIICnDRR in receive mode with the NACKF flag set to 1 does not enable data transmit/receive operation.
Page 822 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface [Clearing conditions] • When data is written to RIICnDRT • When the RIICnCR2.TRS bit is cleared to 0 – When a stop condition is detected – When the RIIC enters receive mode from transmit mode •...
Page 823: Riicnsary - I²C Slave Address Register Y (Y = 0 To 2)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.11 RIICnSARy — I²C Slave Address Register y (y = 0 to 2) Access: RIICnSARy is a 32-bit readable/writable register. RIICnSARyL and RIICnSARyH are 16-bit readable/writable registers. RIICnSARyLL, RIICnSARyLH, RIICnSARyHL, and RIICnSARyHH are 8-bit readable/writable registers. Address: RIICnSAR0: <RIICn_base>...
Page 824 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface SVA[9:1] Bits (7-Bit Address/10-Bit Address Upper Bits) When the 7-bit address format is selected (RIICnSARy.FSy = 0), these bits function as a 7-bit address. When the 10-bit address format is selected (RIICnSARy.FSy = 1), these bits function as a 10-bit address in combination with the SVA0 bit.
Page 825: Riicnbrl - I²C Bus Bit Rate Low-Level Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.12 RIICnBRL — I²C Bus Bit Rate Low-Level Register Access: RIICnBRL is a 32-bit readable/writable register. RIICnBRLL and RIICnBRLH are 16-bit readable/writable registers. RIICnBRLLL, RIICnBRLLH, RIICnBRLHL, and RIICnBRLHH are 8-bit readable/writable registers. Address: RIICnBRL: <RIICn_base>...
Page 826: Riicnbrh - I²C Bus Bit Rate High-Level Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.13 RIICnBRH — I²C Bus Bit Rate High-Level Register Access: RIICnBRH is a 32-bit readable/writable register. RIICnBRHL and RIICnBRHH are 16-bit readable/writable registers. RIICnBRHLL, RIICnBRHLH, RIICnBRHHL, and RIICnBRHHH are 8-bit readable/writable registers. Address: RIICnBRH: <RIICn_base>...
Page 827 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface When SCLE = 1, NFE = 0, CKS = 000 (IICφ = P0φ) Frequency = 1 / {[(BRH + 3) + (BRL + 3)] / IICφ + tr + tf} Duty cycle = {tr + (BRH + 3) / IICφ} / {tr + tf + [(BRH + 3) + (BRL + 3) ] / IICφ} When SCLE = 1, NFE = 1, CKS = 000 (IICφ...
Page 828 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Table 18.20 Minimum Specifiable Value for RIICnBRL and RIICnBRH Minimum Pulse Minimum Pulse Width Width that Specifiable when Minimum Passes through Value for BRH Value is SCLE Digital Filter and BRL Specified ×...
Page 829: Riicndrt - I²C Bus Transmit Data Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.14 RIICnDRT — I²C Bus Transmit Data Register Access: RIICnDRT is a 32-bit readable/writable register. RIICnDRTL and RIICnDRTH are 16-bit readable/writable registers. RIICnDRTLL, RIICnDRTLH, RIICnDRTHL, and RIICnDRTHH are 8-bit readable/writable registers. Address: RIICnDRT: <RIICn_base>...
Page 830: Riicndrr - I²C Bus Receive Data Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.15 RIICnDRR — I²C Bus Receive Data Register Access: RIICnDRR is a 32-bit readable/writable register. RIICnDRRL and RIICnDRRH are 16-bit readable/writable registers. RIICnDRRLL, RIICnDRRLH, RIICnDRRHL, and RIICnDRRHH are 8-bit readable/writable registers. Address: RIICnDRR: <RIICn_base>...
Page 831: Riicndrs - I²C Bus Shift Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.3.16 RIICnDRS — I²C Bus Shift Register Access: This register is not accessible. Address: — Initial Value: 0000 00FF — — — — — — — — — — — —...
Page 832: Interrupt Sources
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.4 Interrupt Sources The RIIC issues eight types of interrupt requests: transmission complete, receive data full, transmit data empty, detection of a stop condition, detection of a start condition, reception of a NACK, arbitration lost, and timeout.
Page 833: Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.5 Operation 18.5.1 Communication Data Format The I C bus format consists of 8-bit data and 1-bit acknowledge (one frame). After a start condition or restart condition is issued, the master device sends the slave address and data direction in the first frame.
Page 834: Initial Settings
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Sr: Restart condition. The master device drives the SDA line low from the high level after the setup time has elapsed with the SCL line at the high level. DATA: Transmitted or received data P: Stop condition.
Page 835: Master Transmit Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.5.3 Master Transmit Operation In master transmit operation, the RIIC outputs the SCL (clock) and transmitted data signals as the master device, and the slave device returns acknowledgements. Figure 18.6 shows an example of usage of master transmission and Figure 18.7 to Figure 18.9 show the timing of operations in master transmission.
Page 836 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Upon detecting the stop condition, the RIIC automatically clears the RIICnCR2.MST and TRS bits to 00 and enters slave receive mode. Furthermore, it automatically clears the RIICnSR2.TDRE and TEND flags to 0, and sets the RIICnSR2.STOP flag in to 1. Clear the RIICnSR2.NACKF and STOP flags to 0.
Page 837 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Master transmission Initial settings Initial settings RIIC0CR2.BBSY = 0? Check I C bus occupation and issue a start condition. RIIC0CR2.ST = 1 RIIC0SR2.NACKF = 0? RIIC0SR2.TDRE = 1? Transmit slave address and W (first byte). Check ACK and set transmit data.
Page 838 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Automatic low-hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF...
Page 839 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface SCLn SDAn A/NA DATA n-2 DATA n-1 DATA n BBSY Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF DATA n-1 RIICnDRT DATA n DATA n-2 RIICnDRS DATA n-1 DATA n XXXX (Initial value/final receive data) RIICnDRR...
Page 840: Master Receive Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.5.4 Master Receive Operation In master receive operation, the RIIC as a master device outputs the SCL (clock) signal, receives data from the slave device, and returns acknowledgements. Since the RIIC must start by sending a slave address to the corresponding slave device, this part of the procedure is performed in master transmit mode, but the subsequent steps are in master receive mode.
Page 841 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface automatically cleared to 0 at the same time. Furthermore, the value of the acknowledgement field received during the ninth cycle of SCL clock is returned as the value set in the RIICnMR3.ACKBT bit.
Page 842 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Master reception Initial settings [1] Initial settings RIICnCR2.BBSY = 0? [2] Check I C bus occupation and issue a start condition. RIICnCR2.ST = 1 RIICnSR2.TDRE = 1? Write data to RIICnDRT [3] Transmit slave address and R and check ACK.
Page 843 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Automatic low hold Master transmit mode Master receive mode (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + R) TDRE Receive data (7-bit address + R) Receive data (DATA 1) TEND...
Page 844 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Automatic low hold (WAIT) Automatic low hold (WAIT) SCLn NACK SDAn DATA n-2 DATA n-1 DATA n BBSY TDRE Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n) TEND RDRF XXXX (last data for transmission [7-bit addresses + R/Upper 10 bits + R])
Page 845 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Master reception [1] Initial settings Initial settings RIICnCR2.BBSY = 0? [2] Check I C bus occupation and issue a start condition. RIICnCR2.ST = 1 RIICnSR2.TDRE = 1? Write data to RIICnDRT [3] Transmit slave address and R and check ACK.
Page 846: Slave Transmit Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.5.5 Slave Transmit Operation In slave transmit operation, the master device outputs the SCL (clock) signal, the RIIC transmits data as a slave device, and the master device returns acknowledgements. Figure 18.15 shows an example of usage of slave transmission and Figure 18.16 and Figure 18.17 show the timing of operations in slave transmission.
Page 847 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Slave transmission [1] Initial settings Initial settings RIICnSR2.NACKF = 0? RIICnSR2.TDRE = 1? Write data to RIICnDRT [2], [3], [4] Check ACK and set transmit data (Checking of ACK not necessary immediately after address is received) All data transmitted? RIICnSR2.TEND = 1?
Page 848 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Slave receive mode Slave transmit mode Automatic low hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF...
Page 849: Slave Receive Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.5.6 Slave Receive Operation In slave receive operation, the master device outputs the SCL clock and transmit data, and the RIIC returns acknowledgements as a slave device. Figure 18.18 shows an example of usage of slave reception and Figure 18.19 and Figure 18.20 show the timing of operations in slave reception.
Page 850 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Slave reception [1] Initial settings Initial settings RIICnSR2.STOP = 0? RIICnSR2.RDRF = 1? RIICnSR2.RDRF = 1? [2], [3], [4] Read receive data (Dummy read first) Read RIICnDRR Read RIICnDRR (last data) All data received? RIICnSR2.STOP = 1? [5] Check stop condition detection...
Page 851 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface SCLn SDAn DATA n-2 DATA n-1 DATA n BBSY TDRE Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n) TEND RDRF AASn RIICnDRT XXXX (Initial value/last data for transmission) RIICnDRS DATA n-2 DATA n-1...
Page 852: Scl Synchronization Circuit
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.6 SCL Synchronization Circuit In generation of the SCL (clock) signal, the RIIC starts counting out the value for width at high level specified in RIICnBRH when it detects a rising edge on the SCL line and drives the SCL line low once counting of the width at high level is complete.
Page 853: Facility For Delaying Sda Output
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.7 Facility for Delaying SDA Output The RIIC module incorporates a facility for delaying output on the SDA line. The delay can be applied to all output (issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals) on the SDA line.
Page 854: Digital Noise-Filter Circuits
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.8 Digital Noise-Filter Circuits Figure 18.23 is a block diagram of the digital noise-filter circuit. When the NFE bit in the RIICnFER register is set to 1, input to the RIICnSCL and RIICnSDA pins are conveyed to the internal circuitry through digital noise-filter circuits.
Page 855: Address Match Detection
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.9 Address Match Detection The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7-bit or 10-bit slave addresses. 18.9.1 Slave-Address Match Detection The RIIC can set three unique slave addresses, and has a slave address detection function for each...
Page 856 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface [10-bit address format: Slave reception] SCLn Upper 2 bits 10-bit slave address (lower 8 bits) Data SDAn BBSY Address match AASy Receive data (lower addresses) TDRE RDRF Read RIICnDRR (Dummy read [lower addresses]) [10-bit address format: Slave transmission] 1 to 8 SCLn...
Page 857: Detection Of The General Call Address
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.9.2 Detection of the General Call Address The RIIC has a facility for detecting the general call address (0000 000 + 0 [W]). This is enabled by setting the RIICnSER.GCE bit to 1. If the address received after a start or restart condition is issued is 0000 000 + 1[R] (start byte), the RIIC recognizes this as the address of a slave device with an “all-zero”...
Page 858: Device-Id Address Detection
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.9.3 Device-ID Address Detection The RIIC module has a facility for detecting device-ID addresses conformant with the I C bus specification (Rev. 03). When the RIIC receives 1111 100 as the first byte after a start condition or restart condition was issued with the RIICnSER.DIDE bit set to 1, the RIIC recognizes the address as a device ID, sets the RIICnSR1.DID flag to 1 on the rising edge of the ninth SCL clock cycle when the following R/W# bit is 0, and then compares the second and subsequent bytes with its own slave...
Page 859 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface [Device-ID reception] 1 to 7 R/W ACK Address BBSY Slave address match AASy Device-ID match (1111 100b + R) Device-ID match (1111 100b + W) Receive data (7-bit address/lower 10 bits) TDRE RDRF Read RIICnDRR...
Page 860: Host Address Detection
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.9.4 Host Address Detection The RIIC has a function to detect the host address while the SMBus is operating. When the RIICnSER.HOAE bit is set to 1 while the RIICnMR3.SMBS bit is 1, the RIIC can detect the host address (0001 000 ) in slave receive mode (RIICnCR2.MST and TRS bits = 00 When the RIIC detects the host address, the RIICnSR1.HOA flag is set to 1 at the rising edge of the...
Page 861: 18.10 Automatically Low-Hold Function For Scl
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.10 Automatically Low-Hold Function for SCL 18.10.1 Function to Prevent Wrong Transmission of Transmit Data If the shift register (RIICnDRS) is empty when data have not been written to the transmit data register (RIICnDRT) with the RIIC in transmission mode (RIICnCR2.TRS bit = 1), the SCL signal is automatically held at the low level over the intervals shown below.
Page 862: Nack Reception Transfer Suspension Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.10.2 NACK Reception Transfer Suspension Function The RIIC has a function to suspend transfer operation when NACK is received in transmit mode (RIICnCR2.TRS bit = 1). This function is enabled when the RIICnFER.NACKE bit is set to 1 (transfer suspension enabled).
Page 863: Function To Prevent Failure To Receive Data
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.10.3 Function to Prevent Failure to Receive Data If response processing is delayed when receive data (RIICnDRR) read is delayed for a period of one transfer frame or more with receive data full (RIICnSR2.RDRF flag = 1) in receive mode (RIICnCR2.TRS = 0), the RIIC holds the SCL line low automatically immediately before the next data is received to prevent failure to receive data.
Page 864 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Automatic low-hold [RDRFS = 0, WAIT = 0] (to prevent failure to receive data) SCLn Data Data Data SDAn RDRF Read RIICnDRR Read RIICnDRR Read RIICnDRR [RDRFS = 0, WAIT = 1] Automatic low- Automatic low-hold (WAIT) Automatic low-hold (WAIT)
Page 865: 18.11 Arbitration-Lost Detection Functions
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.11 Arbitration-Lost Detection Functions In addition to the normal arbitration-lost detection function defined by the I C bus standard, the RIIC has functions to prevent double-issue of a start condition, to detect arbitration-lost during transmission of NACK, and to detect arbitration-lost in slave transmit mode.
Page 866 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface [When slave addresses conflict] Transmit data mismatch Release SCLn/SDA (Arbitration lost) SCLn SDAn SCLn SDAn Data Data BBSY Address match Address mismatch AASy TDRE Clear AL to 0 [When data transmission conflicts after general call address is sent] Transmit data mismatch Release SCLn/SDA (Arbitration-lost)
Page 867: Function To Detect Loss Of Arbitration During Nack Transmission (Nale Bit)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.11.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) The RIIC has a function to cause arbitration to be lost if the internal SDA output level does not match the level on the SDA line (the high output as the internal SDA output;...
Page 868: Slave Arbitration-Lost Detection (Sale Bit)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface transmission processing) necessary if the UDID (Unique Device Identifier) of assign address does not match in the Get UDID (general) processing after the Assign address command. The RIIC detects arbitration-lost during transmission of NACK when the following condition is met with the RIICnFER.NALE bit set to 1 (arbitration-lost detection during NACK transmission enabled).
Page 869: 18.12 Start Condition/Restart Condition/Stop Condition Issuing Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.12 Start Condition/Restart Condition/Stop Condition Issuing Function 18.12.1 Issuing a Start Condition The RIIC issues a start condition when the RIICnCR2.ST bit is set to 1. When the ST bit is set to 1, a start condition issuance request is made and the RIIC issues a start condition when the RIICnCR2.BBSY flag is 0 (bus free).
Page 870 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface [Restart condition issuing operation] [Start condition issuing operation] Hold time Setup time Hold time RIICnBRH RIICnBRL RIICnBRH RIICnBRL RIICnCBRL RIICnBRH RIICnBRL SCLn SCLn Issue start Issue restart condition condition ACK/NACK SDAn SDAn IICφ...
Page 871: Issuing A Stop Condition
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.12.3 Issuing a Stop Condition The RIIC issues a stop condition when the RIICnCR2.SP bit is set to 1. When the SP bit is set to 1, a stop condition issuance request is made and the RIIC issues a stop condition when the RIICnCR2.BBSY flag is 1 (bus busy) and the RIICnCR2.MST bit is 1 (master mode).
Page 872: 18.13 Bus Hanging
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.13 Bus Hanging If the clock signals from the master and slave devices go out of synchronization due to noise or other factors, the I C bus might hang with a fixed level on the SCL line and/or SDA line. As measures against the bus hanging, the RIIC has a timeout function to detect hanging by monitoring the SCL line, a function for the output of an extra SCL clock cycle to release the bus from a hung state due to clock signals being out of synchronization, and the RIIC/internal reset function.
Page 873 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface [Timeout function] Start internal Start internal Start internal Start internal Start internal Start internal counter counter counter counter counter counter Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal counter...
Page 874: Extra Scl Clock Cycle Output Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.13.2 Extra SCL Clock Cycle Output Function In master mode, the RIIC module has a facility for the output of extra SCL (clock) cycles to release the SDA line of the slave device from being held at the low level due to the master being out of synchronization with the slave device.
Page 875: Riic Reset And Internal Reset
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.13.3 RIIC Reset and Internal Reset The RIIC module incorporates a function for resetting itself. There are two types of reset. One is referred to as an RIIC reset; this initializes all registers including the RIICnCR2.BBSY flag. The other is referred to as an internal reset;...
Page 876: 18.14 Smbus Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.14 SMBus Operation The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus communication, set the RIICnMR3.SMBS bit to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the SMBus standard, set the RIICnMR1.CKS[2:0] bits, RIICnCBRH, and RIICnBRL.
Page 877: Smbus Host Notification Protocol/Notify Arp Master
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface For the ACK receive timing (rising edge of the ninth SMBCLK clock cycle), monitor theRIICnSR2. TEND flag in master transmit mode (master transmitter) and the RIICnSR2.RDRF flag in master receive mode (master receiver). For this reason, perform bytewise transmit operation in master transmit mode, and hold the RIICnMR3.RDRFS bit 0 until the byte just before reception of the final byte in master receive mode.
Page 878: 18.15 Reset Function Of Riic
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface 18.15 Reset Function of RIIC The RIIC has chip reset, RIIC reset, and internal reset functions. Table 18.24 lists the scope of each reset and reset conditions. Table 18.24 RIIC Reset Functions (1/2) Start Condition/ RIIC Reset Internal Reset...
Page 879 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 18. I²C Bus Interface Table 18.24 RIIC Reset Functions (2/2) Start Condition/ RIIC Reset Internal Reset Restart Condition Stop Condition Register (ICE = 0, IICRST = 1) (ICE = 1, IICRST = 1) Detection Detection RIICnDRT Initialized...
Page 880: Serial Sound Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Serial Sound Interface The serial sound interface is a module designed to send or receive audio data interface with various devices offering I bus compatibility. It also provides additional modes for other common formats, as well as support for multi-channel mode.
Page 881 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Figure 19.1 shows a block diagram of this module. Peripheral bus Interrupt/DMA request SSIFTDR SSIFRDR Registers Control (8-step FIFO) (8-step FIFO) SSICR circuit SSISR SSIFCR SSIFSR SSITDR SSIRDR Serial audio bus SSITDMR SSIDATA* Shift register...
Page 882: Input/Output Pins
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.2 Input/Output Pins Table 19.1 shows the pin assignments relating to this module. Table 19.1 Pin Assignments Channel Pin Name Description 0, 1, 3 SSISCK0* , SSISCK1* Serial bit clock SSISCK3* SSIWS0* , SSIWS1*...
Page 883: Register Description
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3 Register Description Table 19.2 lists the register configuration. Note that explanation in the text does not refer to the channels. Table 19.2 Register Configuration Access Channel Register Name Abbreviation Initial Value Address Size...
Page 884 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Note 2. To bits 16 and 0 in these registers, only 0 can be written to clear the flags. Other bits are read-only. For details, refer to section 19.3.6, FIFO Status Register (SSIFSR). Note 3.
Page 885: Control Register (Ssicr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.1 Control Register (SSICR) SSICR is a 32-bit readable/writable register that controls the IRQ, selects the polarity status, and sets operating mode. Bit: TUIEN TOIEN RUIEN ROIEN IIEN CHNL[1:0] DWL[2:0] SWL[2:0] Initial value: R/W:...
Page 886 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Initial Bit Name Value Description 21 to 19 DWL[2:0] Data Word Length These bits indicate the number of bits in a data word. 000: 8 bits 001: 16 bits 010: 18 bits 011: 20 bits 100: 22 bits 101: 24 bits...
Page 887 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Initial Bit Name Value Description SDTA Serial Data Alignment 0: Transmitting and receiving in the order of serial data and padding bits 1: Transmitting and receiving in the order of padding bits and serial data PDTA Parallel Data Alignment When the data word length is 32 bits, this configuration field has no meaning.
Page 888 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Initial Bit Name Value Description 7 to 4 CKDV[3:0] 0000 Serial Oversampling Clock Division Ratio Sets the ratio between the oversampling clock (AUDIOφ) and the serial bit clock. When the SCKD bit is 0, the setting of these bits is ignored. The serial bit clock is used in the shift register and is supplied from the SSISCK pin.
Page 889: Status Register (Ssisr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.2 Status Register (SSISR) SSISR consists of status flags indicating the operational status of this module and bits indicating the current channel numbers and word numbers. Bit: TUIRQ TOIRQ RUIRQ ROIRQ IIRQ Initial value: UndefinedUndefined...
Page 890 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Bit Name Initial Value Description IIRQ Idle Mode Interrupt Status Flag This status flag indicates whether this module is in the idle state. This bit is set to 1 regardless of the value of the IIEN bit to allow polling. The interrupt can be masked by clearing IIEN to 0, but cannot be cleared by writing 0 to this bit.
Page 891: Transmit Data Register (Ssitdr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.3 Transmit Data Register (SSITDR) SSITDR is a 32-bit register that stores data to be transmitted. The data for transmission to be stored to SSITDR is automatically transferred from the transmit FIFO data register. Data written to this register is transferred to the shift register upon transmission request.
Page 892: Fifo Control Register (Ssifcr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.5 FIFO Control Register (SSIFCR) SSIFCR is a 32-bit readable/writable register that specifies the data trigger numbers for the transmit and receive FIFO data registers, and enables or disables FIFO data resets and interrupt requests. SSIFCR can always be read or written by the CPU.
Page 893 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Initial Bit Name Value Description Receive Interrupt Enable Enables or disables generation of receive data full interrupt (RXI) requests when the RDF flag in the FIFO status register (SSIFSR) is set to 1 while the FIFO is operating for reception.
Page 894: Fifo Status Register (Ssifsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.6 FIFO Status Register (SSIFSR) SSIFSR contains status flags that indicate the state of operation of the transmit and receive FIFO data registers. Bit: TDC[3:0] Initial value: R/W: R/(W)* Bit: RDC[3:0] Initial value: R/W:...
Page 895 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface Initial Bit Name Value Description R/(W)* Receive Data Full Indicates that, when the FIFO is operating for reception, the received data is transferred to the receive FIFO data register (SSIFRDR) and the number of data bytes in SSIFRDR has become greater than the receive trigger number specified by RTRG[1:0] in the FIFO control register (SSIFCR).
Page 896: Transmit Fifo Data Register (Ssiftdr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.7 Transmit FIFO Data Register (SSIFTDR) SSIFTDR is a FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. On detecting that the transmit data register (SSITDR) is empty, this module transfers the data for transmission written to SSIFTDR to SSITDR to start serial transmission, which can continue until SSIFTDR becomes empty.
Page 897: Tdm Mode Register (Ssitdmr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.9 TDM Mode Register (SSITDMR) SSITDMR is a 32-bit readable/writable register that enables or disables muting of receive data in direct transfer, TDM mode, and WS continue mode. Bit: MUTE Initial value: R/W: Bit:...
Page 898: Fc Control Register (Ssifccr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.10 FC Control Register (SSIFCCR) SSIFCCR is a 32-bit readable/writable register that controls frequency change detection. Bit: FIEN Initial value: R/W: Bit: FCEN Initial value: R/W: Initial Bit Name Value Description 31 to 17 ―...
Page 899: Fc Mode Register (Ssifcmr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.11 FC Mode Register (SSIFCMR) SSIFCMR sets the maximum and minimum allowable numbers of cycles of the peripheral clock 1 (P1φ) for each SSIWS cycle, when frequency change detection is enabled. Bit: MAXV Initial value:...
Page 900: Fc Status Register (Ssifcsr)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.3.12 FC Status Register (SSIFCSR) SSIFCSR consists of the frequency change detection status flag and the bits that indicate the current cycle count of the peripheral clock 1 (P1φ). Bit: FCIRQ Initial value: R/W:...
Page 901: Operation Description
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.4 Operation Description 19.4.1 Bus Format This module can operate as a transmitter or a receiver and can be configured into many serial bus formats in either mode. The bus format can be selected from one of the twelve major modes shown in Table 19.3. Table 19.3 Bus Format for SSIF Module Non-Compression Slave...
Page 902: Non-Compressed Modes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.4.2 Non-Compressed Modes The non-compressed modes support all serial audio streams split into channels. It supports the I S compatible format as well as many more variants on these modes. Slave Receiver This mode allows the module to receive serial data from another device.
Page 903 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface • I S Compatible Format Figure 19.2 and Figure 19.3 show the I S compatible formats without and with padding, respectively. Padding occurs when the data word length is smaller than the system word length. SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00 System word length = data word length SSISCK...
Page 904 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface • MSB-first and Right-aligned Format SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 1 System word length > data word length SSISCK SSIWS Prev.
Page 905 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface (8) Multi-channel Formats Some devices extend the definition of the I S bus specification and allow more than 2 channels to be transferred within two system words. This module supports the transfer of 4, 6, and 8 channels by using the CHNL, SWL and DWL bits only when the system word length (SWL) is greater than or equal to the data word length (DWL) multiplied by channels (CHNL).
Page 906 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface When this module acts as a transmitter, each word written to SSITDR is transmitted to the serial audio bus in the order they are written. When this module acts as a receiver, each word received by the serial audio bus is read from the SSIRDR register in the order they are received.
Page 907 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface (9) Operation Format Configuration Bits Several more configuration bits in non-compressed mode are shown below. These bits are not mutually exclusive, but some combinations may not be useful. These configuration bits are described below with reference to the basic sample format in Figure 19.9. SWL = 6 bits (not attainable in SSI module, demonstration only) DWL = 4 bits (not attainable in SSI module, demonstration only) CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0...
Page 908 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface • Inverted Padding Polarity Same as basic sample format configuration except SPDP = 1 SSISCK SSIWS 1st Channel 2nd Channel SSIDATA TD28 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 TD31 Figure 19.12 Inverted Padding Polarity...
Page 909 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface • Parallel Right-Aligned with Delay Same as basic sample format configuration except PDTA = 1 SSISCK SSIWS 1st Channel 2nd Channel SSIDATA TD3 TD2 TD1 TD0 TD3 TD2 TD1 TD0 Figure 19.16 Parallel Right-Aligned with Delay •...
Page 910: Tdm Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.4.3 TDM Mode TDM mode is provided to enable connection to multi-channel devices for TDM. This mode can be set using the TDM bit in the TDM mode register (SSITDMR). In this mode, the SSIWS signal is high only for system word 1 period and low for the other periods.
Page 911: Ws Continue Mode
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.4.4 WS Continue Mode In WS continue mode, the SSIWS signal continues to be output irrespective whether data transfer is enabled or disabled. This mode can be set using the CONT bit in the TDM mode register (SSITDMR). With this mode enabled, the SSIWS signal does not stop but continues operating even if TEN and REN bits in the control register (SSICR) are both set to 0 (transfer disabled).
Page 912: Transmit Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface (1) Configuration Mode This mode is entered after the module is released from reset. All required configuration fields in the control register should be defined in this mode, before this module is enabled by setting the TEN and REN bits. Setting the TEN and REN bits causes the module to enter the module enabled mode.
Page 913 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface (1) Transmission Using Direct Memory Access Controller Start Define SCKD, SWSD, MUEN, Release from reset, DEL, PDTA, SDTA, SPDP, set SSICR configuration bits. SWSP, SCKP, SWL, DWL, CHNL Set up the direct memory access controller.
Page 914 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface (2) Transmission Using Interrupt-Driven Data Flow Control Start Define SCKD, SWSD, MUEN, Release from reset, DEL, PDTA, SDTA, SPDP, set SSICR configuration bits. SWSP, SCKP, SWL, DWL, CHNL Set up an interrupt controller. Enable error interrupts TUIEN = 1, TOIEN = 1, TIE = 1, and transmit interrupts,...
Page 915: Receive Operation
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.4.7 Receive Operation Like transmission, reception can be controlled either by DMA transfer or interrupt. Figure 19.25 and Figure 19.26 show the flow of operation. When disabling this module, the clock* must be kept supplied to this module until the IIRQ bit indicates that the module is in the idle state.
Page 916 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface (2) Reception Using Interrupt-Driven Data Flow Control Start Define SCKD, SWSD, MUEN, Release from reset, DEL, PDTA, SDTA, SPDP, set SSICR configuration bits. SWSP, SCKP, SWL, DWL, CHNL Set up the interrupt controller. Enable error interrupts RUIEN = 1, ROIEN = 1, RIE = 1, and receive interrupts,...
Page 917: Serial Bit Clock Control
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.4.8 Serial Bit Clock Control This function is used to control and select the clock that is used for the serial bus interface. If the serial bit clock direction is set to input (SCKD = 0), this module is in clock slave mode and the shift register uses the bit clock that was input to the SSISCK pin.
Page 918: Usage Notes
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 19. Serial Sound Interface 19.5 Usage Notes 19.5.1 Limitations from Underflow or Overflow during DMA Operation If an underflow or overflow occurs while the DMA is in operation, the module should be restarted. The transmit and receive buffers in the SSIF consists of 32-bit registers that share the L and R channels.
Page 919: Media Local Bus
20.1 Features • 3-pin interface • A maximum of 50 Mbps of data can be transferred. For details on the functions and registers, contact Renesas Electronics Corporation's sales office. Figure 20.1 shows the block diagram. MediaLB module (MLB) MediaLB RAM...
Page 920: Input/Output Pins
MLB_SIG MediaLB signal information I/O MLB_DAT MediaLB data I/O 20.3 Register Description Table 20.2 shows the register configuration. For details on the registers, contact Renesas Electronics Corporation's sales office. Table 20.2 Register Configuration Initial Access Register Name Abbreviation R/W Value...
Page 921: Can Interface
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface CAN Interface This section gives an overall description of the CAN interface (RS-CAN). The first section describes the features specific to this LSI, including the number of units and the register base addresses. The subsequent sections describe the RS-CAN’s functions and registers. 21.1 Overview 21.1.1...
Page 922: Register Addresses
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.1.2 Register addresses RS-CAN base addresses are listed in the following table. RS-CAN register addresses are given as offsets from the base addresses. Table 21.4 Register base address Base Address Name Base Address <RSCAN0_base>...
Page 923: Interrupts
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.1.4 Interrupts The Controller Area Network (RS-CAN) can generate the interrupt requests shown in the following table. Table 21.7 RS-CAN interrupt requests Unit Interrupt Name Outline Interrupt ID DMA Trigger Number RSCAN0 INTRCANGERR CAN global error interrupt...
Page 924: Function
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.2 Function This LSI incorporates one unit of the CAN interface (RS-CAN) which consists of two channels (CAN0 and CAN1) of the CAN controller conforming to the ISO11898-1 specifications. Table 21.9 shows the RSCAN module specifications.
Page 925 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.9 RS-CAN Module Specifications (2/2) Item Specification Transmit history function Stores the history information of transmitted messages. Gateway function A received message is automatically routed to a different channel. Bus off recovery mode Selects the method for returning from bus off state.
Page 926: Block Diagram
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.2.1 Block Diagram Peripheral bus CAN-related registers Receive rule table RAM Acceptance filter CAN0RX Protocol Baud rate controller prescaler ID priority CAN0TX (BRP[9:0]) transmission FIFO RAM controller CANmRX Timer Protocol Baud rate controller prescaler Buffer RAM...
Page 927: Registers
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3 Registers Table 21.10 lists the registers of the RS-CAN module.n = 0, 1. Table 21.10 List of RS-CAN Module Registers (1/12) Access Register Name Symbol After Reset Address Size Channel 0 configuration register RSCAN0C0CFG 0000 0000 <RSCAN0_base>...
Page 928 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (2/12) Access Register Name Symbol After Reset Address Size Transmit/receive FIFO buffer configuration and control RSCAN0CFCC1 0000 0000 <RSCAN0_base> + 011C 8, 16, 32 register 1 Transmit/receive FIFO buffer configuration and control RSCAN0CFCC2...
Page 929 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (3/12) Access Register Name Symbol After Reset Address Size Transmit buffer control register 20 RSCAN0TMC20 <RSCAN0_base> + 0264 Transmit buffer control register 21 RSCAN0TMC21 <RSCAN0_base>...
Page 930 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (4/12) Access Register Name Symbol After Reset Address Size Transmit buffer transmit abort status register 0 RSCAN0TMTASTS0 0000 0000 <RSCAN0_base> + 0380 8, 16, 32 Transmit buffer interrupt enable configuration register 0 RSCAN0TMIEC0 0000 0000...
Page 931 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (5/12) Access Register Name Symbol After Reset Address Size Receive rule mask register 7 RSCAN0GAFLM7 0000 0000 <RSCAN0_base> + 0574 8, 16, 32 Receive rule pointer 0 register 7 RSCAN0GAFLP07 0000 0000 <RSCAN0_base>...
Page 932 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (6/12) Access Register Name Symbol After Reset Address Size Receive buffer ID register 3 RSCAN0RMID3 0000 0000 <RSCAN0_base> + 0630 8, 16, 32 Receive buffer pointer register 3 RSCAN0RMPTR3 0000 0000 <RSCAN0_base>...
Page 933 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (7/12) Access Register Name Symbol After Reset Address Size Receive buffer data field 1 register 14 RSCAN0RMDF114 0000 0000 <RSCAN0_base> + 06EC 8, 16, 32 Receive buffer ID register 15 RSCAN0RMID15 0000 0000...
Page 934 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (8/12) Access Register Name Symbol After Reset Address Size Receive buffer data field 0 register 26 RSCAN0RMDF026 0000 0000 <RSCAN0_base> + 07A8 8, 16, 32 Receive buffer data field 1 register 26 RSCAN0RMDF126 0000 0000...
Page 935 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (9/12) Access Register Name Symbol After Reset Address Size Receive FIFO buffer access pointer register 6 RSCAN0RFPTR6 0000 0000 <RSCAN0_base> + 0E64 8, 16, 32 Receive FIFO buffer access data field 0 register 6 RSCAN0RFDF06 0000 0000...
Page 936 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (10/12) Access Register Name Symbol After Reset Address Size Transmit buffer ID register 4 RSCAN0TMID4 0000 0000 <RSCAN0_base> + 1040 8, 16, 32 Transmit buffer pointer register 4 RSCAN0TMPTR4 0000 0000 <RSCAN0_base>...
Page 937 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (11/12) Access Register Name Symbol After Reset Address Size Transmit buffer data field 1 register 15 RSCAN0TMDF115 0000 0000 <RSCAN0_base> + 10FC 8, 16, 32 Transmit buffer ID register 16 RSCAN0TMID16 0000 0000...
Page 938 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.10 List of RS-CAN Module Registers (12/12) Access Register Name Symbol After Reset Address Size Transmit buffer data field 0 register 27 RSCAN0TMDF027 0000 0000 <RSCAN0_base> + 11B8 8, 16, 32 Transmit buffer data field 1 register 27 RSCAN0TMDF127 0000 0000...
Page 939 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.12 Transmit/Receive FIFO Buffer k Allocated to Each Channel CANm Transmit/receive FIFO buffer Transmit/receive FIFO buffer 3 × m + 0 Transmit/receive FIFO buffer 3 × m + 1 Transmit/receive FIFO buffer 3 × m + 2 Table 21.13 Transmit Buffer p Linked to the Transmit/Receive FIFO Buffer by the Setting of Bits CFTML[3:0]...
Page 940: Rscan0Cmcfg - Channel Configuration Register (M = 0 Or 1)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.1 RSCAN0CmCFG — Channel Configuration Register (m = 0 or 1) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0000 + (m * 0010 Initial value: 0000 0000 —...
Page 941 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Modify the RSCAN0CmCFG register in channel reset mode or channel halt mode. Set this register before requesting a transition to channel communication mode or channel wait mode. For a description of the bit timing parameters and settings, see Section 21.10.1, Initial Settings. SJW[1:0] Bits These bits are used to specify a Tq value for the resynchronization jump width.
Page 942: Rscan0Cmctr - Channel Control Register (M = 0 Or 1)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.2 RSCAN0CmCTR — Channel Control Register (m = 0 or 1) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0004 + (m * 0010 Initial value: 0000 0005 —...
Page 943 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.16 RSCAN0CmCTR register contents (2/2) Bit Position Bit Name Function BOEIE Bus Off Entry Interrupt Enable 0: Bus off entry interrupt is disabled. 1: Bus off entry interrupt is enabled. EPIE Error Passive Interrupt Enable 0: Error passive interrupt is disabled.
Page 944 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface BOM[1:0] Bits These bits are used to select the bus off recovery mode of the RS-CAN module. When the BOM[1:0] bits are set to 00 , return from the bus off state to the error active state is compliant with the CAN specifications.
Page 945 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface BORIE Bit When the BORF flag in the RSCAN0CmERFL register is set to 1 with the BORIE bit set to 1, an error interrupt request is generated. Modify this bit only in channel reset mode. BOEIE Bit When the BOEF flag in the RSCAN0CmERFL register is set to 1 with the BOEIE bit set to 1, an error interrupt request is generated.
Page 946: Rscan0Cmsts - Channel Status Register (M = 0 Or 1)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.3 RSCAN0CmSTS — Channel Status Register (m = 0 or 1) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0008 + (m * 0010 Initial value: 0000 0005 TEC[7:0] REC[7:0]...
Page 947 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface REC[7:0] Bits These bits contain the receive error counter value. For receive error counter increment/decrement conditions, see the CAN specifications (ISO11898-1). These bits are cleared to 0 in channel reset mode. COMSTS Flag This bit indicates that communication is ready.
Page 948: Rscan0Cmerfl - Channel Error Flag Register (M = 0 Or 1)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.4 RSCAN0CmERFL — Channel Error Flag Register (m = 0 or 1) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 000C + (m * 0010 Initial value: 0000 0000 —...
Page 949 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.18 RSCAN0CmERFL register contents (2/2) Bit Position Bit Name Function OVLF Overload Flag 0: No overload is detected. 1: Overload is detected. BORF Bus Off Recovery Flag 0: No bus off recovery is detected. 1: Bus off recovery is detected.
Page 950 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface FERR Flag This flag is set to 1 when a form error has been detected. SERR Flag This flag is set to 1 when a stuff error has been detected. ALF Flag This flag is set to 1 when an arbitration-lost has been detected.
Page 951 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface EPF Flag This flag becomes 1 when the error passive state is reached (REC[7:0] or TEC[7:0] value > 127). This flag becomes 1 only when the REC[7:0] or TEC[7:0] value first exceeds 127. Therefore, if the program writes 0 to this flag while the value of REC[7:0] or TEC[7:0] remains over 127, this bit is not set to 1 until both REC [7:0] and TEC[7:0] values become 127 or less and then the REC[7:0] or TEC[7:0] value exceeds 127 again.
Page 952: Rscan0Gcfg - Global Configuration Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.5 RSCAN0GCFG — Global Configuration Register Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0084 Initial value: 0000 0000 ITRCP Initial value TSBTCS[2:0] TSSS TSP[3:0] — —...
Page 953 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.19 RSCAN0GCFG register contents (2/2) Bit Position Bit Name Function Mirror Function Enable 0: Mirror function is disabled. 1: Mirror function is enabled. DLC Replacement Enable 0: DLC replacement is disabled. 1: DLC replacement is enabled.
Page 954 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface DRE Bit When the DRE bit is set to 1, the DLC value of the receive rule is stored in the buffer instead of the DLC value of the received message after the DLC value has passed through the DLC filter. In this case, a value of 00 is stored in each data byte beyond the first n bytes, where n is the DLC value of the receive rule.
Page 955: Rscan0Gctr - Global Control Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.6 RSCAN0GCTR — Global Control Register Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0088 Initial value: 0000 0005 — — — — — — — —...
Page 956 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface MEIE Bit When the MEIE bit is set to 1 and the MES flag in the RSCAN0GERFL register is set to 1, an interrupt request is generated. Modify this bit only in global reset mode. DEIE Bit When the DEIE bit is set to 1 and the DEF flag in the RSCAN0GERFL register is set to 1, an interrupt request is generated.
Page 957: Rscan0Gsts - Global Status Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.7 RSCAN0GSTS — Global Status Register Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 008C Initial value: 0000 000D — — — — — — — —...
Page 958 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface GRSTSTS Flag This flag is set to 1 when the CAN module has transitioned to global reset mode, and is cleared to 0 when the CAN module has exited global reset mode. This flag remains 1 even when the CAN module has transitioned from global reset mode to global stop mode.
Page 959: Rscan0Gerfl - Global Error Flag Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.8 RSCAN0GERFL — Global Error Flag Register Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0090 Initial value: 0000 0000 — — — — — — —...
Page 960: Rscan0Gtintsts0 - Global Tx Interrupt Status Register 0
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.9 RSCAN0GTINTSTS0 — Global TX Interrupt Status Register 0 Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0460 Initial value: 0000 0000 — — — — —...
Page 961 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface TSIFm Bits The TSIFm bit is set to 1 when the TMIE bit in the RSCAN0TMIECy register is set to 1 (transmit buffer interrupt enabled) and the TMTRF[1:0] flags in the RSCAN0TMSTSp register are set to 10 (transmit completed without abort request) or 11 (transmit completed with abort request).
Page 962: Rscan0Gtsc - Global Timestamp Counter Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.10 RSCAN0GTSC — Global Timestamp Counter Register Access: Can be read in 8-, 16- and 32-bit units Address: <RSCAN0_base> + 0094 Initial value: 0000 0000 — — — — — — —...
Page 963: Rscan0Gaflectr - Receive Rule Entry Control Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.11 RSCAN0GAFLECTR — Receive Rule Entry Control Register Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0098 Initial value: 0000 0000 — — — — — —...
Page 964: Rscan0Gaflcfg0 - Receive Rule Configuration Register 0
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.12 RSCAN0GAFLCFG0 — Receive Rule Configuration Register 0 Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 009C Initial value: 0000 0000 RNC0[7:0] RNC1[7:0] Initial value — —...
Page 965: Rscan0Gaflidj - Receive Rule Id Register (J = 0 To 15)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.13 RSCAN0GAFLIDj — Receive Rule ID Register (j = 0 to 15) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0500 + (j * 0010 Initial value: 0000 0000 GAFLID GAFLR...
Page 966 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface GAFLLB Bit When this bit is set to 0, data processing using the receive rule is performed when receiving messages transmitted from another CAN node. When this bit is set to 1 when the mirror function is used, data processing using the receive rule is performed when the CAN node is receiving its own transmitted messages.
Page 967: Rscan0Gaflmj - Receive Rule Mask Register (J = 0 To 15)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.14 RSCAN0GAFLMj — Receive Rule Mask Register (j = 0 to 15) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0504 + (j * 0010 Initial value: 0000 0000 GAFLID GAFLR...
Page 968: Rscan0Gaflp0J - Receive Rule Pointer 0 Register (J = 0 To 15)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.15 RSCAN0GAFLP0j — Receive Rule Pointer 0 Register (j = 0 to 15) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0508 + (j * 0010 Initial value: 0000 0000 GAFLDLC[3:0]...
Page 969 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface GAFLRMV Bit When this bit is set to 1, receive messages that have passed through the filter are stored in the receive buffer selected by the GAFLRMDP[6:0] bits. GAFLRMDP[6:0] Bits These bits are used to select the number of the receive buffer that stores receive messages that have passed through the filter when the GAFLRMV bit is set to 1.
Page 970: Rscan0Gaflp1J - Receive Rule Pointer 1 Register (J = 0 To 15)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.16 RSCAN0GAFLP1j — Receive Rule Pointer 1 Register (j = 0 to 15) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 050C + (j * 0010 Initial value: 0000 0000 —...
Page 971: Rscan0Rmnb - Receive Buffer Number Register
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.17 RSCAN0RMNB — Receive Buffer Number Register Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 00A4 Initial value: 0000 0000 — — — — — — —...
Page 972: Rscan0Rmndy - Receive Buffer New Data Register Y (Y = 0)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.18 RSCAN0RMNDy — Receive Buffer New Data Register y (y = 0) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 00A8 + (y * 0004 Initial value: 0000 0000 RMNSq (q = y ×...
Page 973: Rscan0Rmidq - Receive Buffer Id Register (Q = 0 To 31)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.19 RSCAN0RMIDq — Receive Buffer ID Register (q = 0 to 31) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0600 + (q * 0010 Initial value: 0000 0000 RMIDE RMRTR —...
Page 974: Rscan0Rmptrq - Receive Buffer Pointer Register (Q = 0 To 31)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.20 RSCAN0RMPTRq — Receive Buffer Pointer Register (q = 0 to 31) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0604 + (q * 0010 Initial value: 0000 0000 RMDLC[3:0] RMPTR[11:0]...
Page 975: Rscan0Rmdf0Q - Receive Buffer Data Field 0 Register (Q = 0 To 31)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.21 RSCAN0RMDF0q — Receive Buffer Data Field 0 Register (q = 0 to 31) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0608 + (q * 0010 Initial value: 0000 0000 RMDB3[7:0]...
Page 976: Rscan0Rmdf1Q - Receive Buffer Data Field 1 Register (Q = 0 To 31)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.22 RSCAN0RMDF1q — Receive Buffer Data Field 1 Register (q = 0 to 31) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 060C + (q * 0010 Initial value: 0000 0000 RMDB7[7:0]...
Page 977: Rscan0Rfccx - Receive Fifo Buffer Configuration And Control Register (X = 0 To 7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.23 RSCAN0RFCCx — Receive FIFO Buffer Configuration and Control Register (x = 0 to 7) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 00B8 + (x * 0004 Initial value: 0000 0000 —...
Page 978 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface RFIGCV[2:0] Bits These bits are used to specify the number of received messages for generating a receive FIFO interrupt request when the RFIM bit is set to 0 with a fraction for the total number of buffers (the setting of RFDC[2:0]).
Page 979: Rscan0Rfstsx - Receive Fifo Buffer Status Register (X = 0 To 7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.24 RSCAN0RFSTSx — Receive FIFO Buffer Status Register (x = 0 to 7) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 00D8 + (x * 0004 Initial value: 0000 0001 —...
Page 980 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface RFIF Flag This flag is set to 1 when the receive FIFO interrupt request generation conditions set by the RFIGCV[2:0] bits and the RFIM bit in the RSCAN0RFCCx register are met. This flag is cleared to 0 in global reset mode or by writing 0 to this flag.
Page 981: Rscan0Rfpctrx - Receive Fifo Buffer Pointer Control Register (X = 0 To 7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.25 RSCAN0RFPCTRx — Receive FIFO Buffer Pointer Control Register (x = 0 to 7) Access: Can be written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 00F8 + (x * 0004 Initial value: 0000 0000 —...
Page 982: Rscan0Rfidx - Receive Fifo Buffer Access Id Register (X = 0 To 7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.26 RSCAN0RFIDx — Receive FIFO Buffer Access ID Register (x = 0 to 7) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0E00 + (x * 0010 Initial value: 0000 0000 RFIDE RFRTR...
Page 983: Rscan0Rfptrx - Receive Fifo Buffer Access Pointer Register (X = 0 To 7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.27 RSCAN0RFPTRx — Receive FIFO Buffer Access Pointer Register (x = 0 to 7) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0E04 + (x * 0010 Initial value: 0000 0000 RFDLC[3:0]...
Page 984: Rscan0Rfdf0X - Receive Fifo Buffer Access Data Field 0 Register (X = 0 To 7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.28 RSCAN0RFDF0x — Receive FIFO Buffer Access Data Field 0 Register (x = 0 to 7) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0E08 + (x * 0010 Initial value: 0000 0000 RFDB3[7:0]...
Page 985: Rscan0Rfdf1X - Receive Fifo Buffer Access Data Field 1 Register (X = 0 To 7)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.29 RSCAN0RFDF1x — Receive FIFO Buffer Access Data Field 1 Register (x = 0 to 7) Access: Can be read in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0E0C + (x * 0010 Initial value: 0000 0000 RFDB7[7:0]...
Page 986: Rscan0Cfcck - Transmit/Receive Fifo Buffer Configuration And Control Register K (K = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.30 RSCAN0CFCCk — Transmit/receive FIFO buffer Configuration and Control Register k (k = 0 to 5) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0118 + (k * 0004 Initial value: 0000 0000 CFITT[7:0]...
Page 987 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Table 21.44 RSCAN0CFCCk register contents (2/2) Bit Position Bit Name Function CFIM Transmit/Receive FIFO Interrupt Source Select • Receive mode/gateway mode When the number of received messages has met the condition set by the CFIGCV[2:0] bits, a FIFO receive interrupt request is generated.
Page 988 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface Setting the CFDC[2:0] bits to 001 or more enables the setting of the CFTML[3:0] bits. Do not link to any transmit buffer which is already allocated to a transmit queue on the identical channel or to another transmit/receive FIFO buffer.
Page 989 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface CFRXIE Bit When this bit is set to 1 and the CFRXIF flag in the RSCAN0CFSTSk register is set to 1, a transmit/ receive FIFO receive interrupt request is generated. Modify this bit with the CFE bit set to 0. CFE Bit Setting this bit to 1 makes transmit/receive FIFO buffers available.
Page 990: Rscan0Cfstsk - Transmit/Receive Fifo Buffer Status Register (K = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.31 RSCAN0CFSTSk — Transmit/receive FIFO buffer Status Register (k = 0 to 5) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0178 + (k * 0004 Initial value: 0000 0000 —...
Page 991 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface CFMC[7:0] Bits The CFMC[7:0] bits indicate the following values that depend on the setting of the CFM[1:0] bits in the RSCAN0CFCCk register. • When CFM[1:0] value is 01 (transmit mode): Number of untransmitted messages in the buffer •...
Page 992 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface • When the CFM[1:0] bits are set to 01 or 10 : In channel reset mode Write 0 to this flag in global operating mode or global test mode CFFLL Flag The CFFLL flag is set to 1 when any of the following conditions is met.
Page 993: Rscan0Cfpctrk - Transmit/Receive Fifo Buffer Pointer Control Register (K = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.32 RSCAN0CFPCTRk — Transmit/receive FIFO buffer Pointer Control Register (k = 0 to 5) Access: Can be written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 01D8 + (k * 0004 Initial value: 0000 0000 —...
Page 994 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface • Transmit mode (CFM[1:0] value in the RSCAN0CFCCk register is 01 Writing FF to the CFPC[7:0] bits stores the data written to the RSCAN0CFIDk, RSCAN0CFPTRk, RSCAN0CFDF0k, and RSCAN0CFDF1k registers in the transmit/receive FIFO buffer and moves the write pointer to the next stage of the transmit/receive FIFO buffer.
Page 995: Rscan0Cfidk - Transmit/Receive Fifo Buffer Access Id Register (K = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.33 RSCAN0CFIDk — Transmit/receive FIFO buffer Access ID Register (k = 0 to 5) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0E80 + (k * 0010 Initial value: 0000 0000 CFIDE CFRTR THLEN...
Page 996 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface CFRTR Bit This bit indicates the data format (data frame or remote frame) of the received message stored in the transmit/receive FIFO buffer when the CFM[1:0] value is 00 . When the CFM[1:0] value is 01 , this bit is used to set the data format of the message to be transmitted from the transmit/receive FIFO buffer.
Page 997: Rscan0Cfptrk - Transmit/Receive Fifo Buffer Access Pointer Register (K = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.34 RSCAN0CFPTRk — Transmit/receive FIFO buffer Access Pointer Register (k = 0 to 5) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0E84 + (k * 0010 Initial value: 0000 0000 CFDLC[3:0]...
Page 998 RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface CFDLC[3:0] Bits These bits indicate the data length of the received message stored in the transmit/receive FIFO buffer when the CFM[1:0] value is 00 . When the CFM[1:0] value is 01 , these bits are used to set the data length of the message to be transmitted from the transmit/receive FIFO buffer.
Page 999: Rscan0Cfdf0K - Transmit/Receive Fifo Buffer Access Data Field 0 Register (K = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.35 RSCAN0CFDF0k — Transmit/receive FIFO buffer Access Data Field 0 Register (k = 0 to 5) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0E88 + (k * 0010 Initial value: 0000 0000 CFDB3[7:0]...
Page 1000: Rscan0Cfdf1K - Transmit/Receive Fifo Buffer Access Data Field 1 Register (K = 0 To 5)
RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group 21. CAN Interface 21.3.36 RSCAN0CFDF1k — Transmit/receive FIFO buffer Access Data Field 1 Register (k = 0 to 5) Access: Can be read/written in 8-, 16-, and 32-bit units Address: <RSCAN0_base> + 0E8C + (k * 0010 Initial value: 0000 0000 CFDB7[7:0]...

This manual is also suitable for:

Rz/a1 series Rz/a1lu series Rz/a1lc series