North Main Bus; Configuration; Features - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.2

North Main Bus

5.2.1

Configuration

Various peripheral modules are connected to the north main bus. Figure 5.2 shows the configuration of the north main
bus.
Direct
Cortex-A9
memory access
controller
SLV0 SLV1
Write Write
buffer buffer
Peripheral Peripheral
module module
Figure 5.2 North Main Bus Configuration
5.2.2

Features

Table 5.1 shows the features of the north main bus.
Table 5.1 North Main Bus
Item
Bus protocol
Bus system configuration
Bus clock frequency
Bus width
Arbitration
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
JPEG Media
Ethernet
codec local
controller
unit* 2 bus* 1
Write
buffer
1
*
SLV2 SLV3
Write Write
buffer buffer
Write
memory access
buffer
AHB32IC3 bus
Peripheral Peripheral
module module
Peripheral Peripheral
module module
Capture
CoreSight engine
unit
Write
buffer
North main bus
SLV4
OpenVG
AXI64IC2 bus
compliant
Direct
Interrupt
On-chip
controller ROM
controller
Description
®
AMBA AXI protocol
AXI interconnect with multi-layer configuration for all channels
Bφ
64 bits
Round robin
5. LSI Internal Bus
SLV5 SLV6 SLV7 SLV8
TM
-
Write
buffer
Renesas
graphics
processor
Bus Bus
bridge 1 bridge 2
Peripheral
module
South main bus
Note 1. RZ/A1L only
Note 2. RZ/A1LU only
5-2