Input/Output Pins - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.3

Input/Output Pins

Table 17.1 shows the pin configuration for one channel.
Table 17.1 Pin Configuration
Port
Common
0
1
Note: n represents a channel number (0). In the text, the channel number is omitted.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Pin Name Symbol
Clock pin SPBCLK_n
Slave select pin SPBSSL_n
Data 0 pin SPBMO0_n/
SPBIO00_n
Port 0 data 1 pin SPBMI0_n/
SPBIO10_n
Port 0 data 2 pin SPBIO20_n
Port 0 data 3 pin SPBIO30_n
Port 1 data 0 pin SPBMO1_n/
SPBIO01_n
Port 1 data 1 pin SPBMI1_n/
SPBIO11_n
Port 1 data 2 pin SPBIO21_n
Port 1 data 3 pin SPBIO31_n
17. SPI Multi I/O Bus Controller
I/O Function
Output Clock output
Output Slave selection
I/O Port 0 master transmit
data/data 0
I/O Port 0 master input data/
data 1
I/O Port 0 data 2
I/O Port 0 data 3
I/O Port 1 master transmit
data/data 0
I/O Port 1 master input data/
data 1
I/O Port 1 data 2
I/O Port 1 data 3
17-3