Block Diagram - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.2.2

Block Diagram

Output
RIICnSCL
control
Noise
canceller
NF[1:0]
Output
RIICnSDA
control
Noise
canceller
NF[1:0]
Figure 18.1
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
FMPE
SCL0, SDA0
NFE
PS
IICφ, IICφ/2
SDA output delay control
ACKBT
ACK output circuit
FMPE
NACKE
NACK decision/
ACK reception circuit
Arbitration decision
NFE
circuit
MALE, NALE, SALE
Bus state decision
circuit
Block Diagram of RIIC
Transfer clock
CLO
IICRST
Transmission/
reception control
ST, RS, SP
circuit
DLCS
WAIT, RDRFS
SDDL[2:0]
RIICnDRT
RIICnDRS
RIICnDRR
TMOE
TMOS, TMOH, TMOL
Timeout circuit
(INTRIICTEI, INTRIICRI, INTRIICTI, INTRIICSPI, INTRIICSTI, INTRIICNAKI, INTRIICALI, INTRIICTMOI)
18. I²C Bus Interface
P0φ
CKS[2:0]
PS
RIICnMR1
BC[2:0]
RIICnBRH
generator
RIICnBRL
SCLE
SCLI
RIICnCR1
SDAI
RIICnCR2
BBSY, MST, TRS
RIICnFER
RIICnMR2
RIICnMR3
ACKBR
RIICnSAR0
RIICnSAR1
RIICnSAR2
Address comparator
RIICnSR1
RIICnSER
NACKF
RIICnSR2
TMOF
RIICnIER
Interrupt generator
Interrupt request
18-5

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Rz/a1 seriesRz/a1lu seriesRz/a1lc series

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