Rscan0Gaflmj - Receive Rule Mask Register (J = 0 To 15) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.14 RSCAN0GAFLMj — Receive Rule Mask Register (j = 0 to 15)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0504
Initial value: 0000 0000
Bit 31 30 29
GAFLID GAFLR
—
EM TRM
Initial value 0 0 0
R/W R/W R/W R
Bit 15 14 13
0 0 0
Initial value
R/W R/W R/W R/W
Table 21.28
Bit Position
31
30
29
28 to 0
Modify the RSCAN0GAFLMj register when the AFLDAE bit in the RSCAN0GAFLECTR register is
set to 1 (receive rule table write is enabled) in global reset mode.
GAFLIDEM Bit
When this bit is set to 1, filter processing is performed only for messages of the ID format specified by
the GAFLIDE bit in the RSCAN0GAFLIDj register.
When this bit is cleared to 0, the IDs of all the receive messages and the specified IDs are regarded as
matched. To set the GAFLIDEM bit to 0, set the GAFLIDM[28:0] bits to all 0 at the same time.
GAFLRTRM Bit
This bit is used to mask the RTR bit of the receive rule.
GAFLIDM[28:0] Bits
These bits are used to mask the corresponding ID bit of the receive rule.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (j * 0010 )
H H
H
28 27 26
0 0 0
R/W R/W R/W
12 11 10
0 0 0
R/W R/W R/W
RSCAN0GAFLMj register contents
Bit Name Function
GAFLIDEM IDE Mask
GAFLRTRM RTR Mask
Reserved This bit is always read as 0. The write value should always be 0.
GAFLIDM[28:0] ID Mask
25 24 23 22
GAFLIDM[28:16]
0 0 0 0
R/W R/W R/W R/W
9 8 7 6
GAFLIDM[15:0]
0 0 0 0
R/W R/W R/W R/W
0: The IDE bit is not compared.
1: The IDE bit is compared.
0: The RTR bit is not compared.
1: The RTR bit is compared
0: The corresponding ID bit is not compared.
1: The corresponding ID bit is compared.
21. CAN Interface
21 20 19 18
0 0 0 0
R/W R/W R/W R/W
5 4 3 2
0 0 0 0
R/W R/W R/W R/W
17 16
0 0
R/W R/W
1 0
0 0
R/W R/W
21-47