Burst Rom (Clocked Asynchronous) Interface - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.5.7

Burst ROM (Clocked Asynchronous) Interface

The burst ROM (clocked asynchronous) interface is used to access a memory with a high-speed read function using a
method of address switching called the burst mode or page mode. In a burst ROM (clocked asynchronous) interface,
basically the same access as the normal space is performed, but the 2nd and subsequent access cycles are performed only
by changing the address, without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent access
cycles, addresses are changed at the falling edge of the CKIO.
For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is inserted. For the 2nd
and subsequent access cycles, the number of wait cycles specified by the BW1 and BW0 bits in CSnWCR is inserted.
In the access to the burst ROM (clocked asynchronous), the BS signal is asserted only to the first access cycle. An
external wait input is valid only to the first access cycle.
In the single access or write access that does not perform the burst operation in the burst ROM (clocked asynchronous)
interface, access timing is same as a normal space.
Table 8.17 lists a relationship between bus width, access size, and the number of bursts. Figure 8.33 shows a timing chart.
Table 8.17 Relationship between Bus Width, Access Size, and Number of Bursts
Bus Width Access Size
8 bits 8 bits
16 bits
32 bits
16 bytes
32 bytes
64 bytes
16 bits 8 bits
16 bits
32 bits
16 bytes
32 bytes
64 bytes
32 bits 8 bits
16 bits
32 bits
16 bytes
32 bytes
64 bytes
Note 1. When the bus width is 16 bits, the access size is 16 bytes or more, and the BST[1:0] bits in CSnWCR are 10, the number of
bursts and access count depend on the access start address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At
address H'xxx4 or H'xxxC, 2-4-2 burst access is performed.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
CSnWCR. BST[1:0] Bits
Not affected
Not affected
Not affected
00
01
00
01
00
01
Not affected
Not affected
Not affected
00
01
1
10*
00
01
1
10*
00
01
10* 1
Not affected
Not affected
Not affected
Not affected
Not affected
Not affected
8. Bus State Controller
Number of Bursts Access Count
1 1
2 1
4 1
16 1
4 4
16 2
4 8
16 4
4 16
1 1
1 1
2 1
8 1
2 4
4 2
2, 4, 2 3
8 2
2 8
4 4
2, 4, 2 6
8 4
2 16
4 8
2, 4, 2 12
1 1
1 1
1 1
4 1
4 2
4 4
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