Rscan0Gtstcfg - Global Test Configuration Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.61 RSCAN0GTSTCFG — Global Test Configuration Register
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0468
Initial value: 0000 0000
H
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.80
Bit Position
31 to 2
1
0
Modify the RSCAN0GTSTCFG register only in global test mode.
C1ICBCE Bit
Setting this bit to 1 enables the channel 1 inter-channel communication test.
C0ICBCE Bit
Setting this bit to 1 enables the channel 0 inter-channel communication test.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
28 27 26 25
— — — —
0 0 0 0
R R R R
12 11 10 9
— — — —
0 0 0 0
R R R R
RSCAN0GTSTCFG register contents
Bit Name Function
Reserved These bits are always read as 0. The write value should always be 0.
C1ICBCE CAN1 Inter-Channel Communication Test Enable
0: CAN1 inter-channel communication test is disabled.
1: CAN1 inter-channel communication test is enabled.
C0ICBCE CAN0 Inter-Channel Communication Test Enable
0: CAN0 inter-channel communication test is disabled.
1: CAN0 inter-channel communication test is enabled.
24 23 22 21
— — — —
0 0 0 0
R R R R
8 7 6 5
— — — —
0 0 0 0
R R R R
21. CAN Interface
20 19 18 17
— — — —
0 0 0 0
R R R R
4 3 2 1
C1ICBC
— — —
E
0 0 0 0
R R R R/W
16
—
0
R
0
C0ICBC
E
0
R/W
21-111